JPH0282554A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a contact resistance against a region to be electrically connected and to improve arrangement freedom of a conductive material at the same time by increasing an area of an opening section relatively and by reducing a contact area of a first conductive material and a second conductive material relatively. CONSTITUTION:Contact holes 14a, 14b are formed in an insulating film 12, wide along a gate electrode 18. A conductive material 15 such as polycrystalline Si is deposited all over a semiconductor substrate 11 through CVD and etched- back to bury the conductive material 15 in the contact holes 14a, 14b. Then another insulating film 21 is formed through CVD, oxidation, etc., on the insulating film 12 and the conductive material 15, and contact holes 22a, 22b are formed at an approximately same place and area as the contact holes 14a, 14b. Evaporation of Al and patterning are carried out to form Al wirings 16a, 16b, 17. Both of reduction of contact resistance against source drain regions 13a, 13b and increase of arrangement freedom of an Al wiring 17 can be realized at the same time in this way.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is characterized in that a first conductive material is embedded in an opening of an insulating film, and a second conductive material is connected to the first conductive material. The present invention relates to semiconductor devices.

[Summary of the invention]

In the semiconductor device as described above, the present invention makes the area of the opening relatively large and the contact area between the first conductive material and the second conductive material relatively small. The present invention is designed to achieve both a reduction in contact resistance for a region to be connected and an increase in the degree of freedom in arranging a conductive material on an insulating film.

[Prior Art] With the miniaturization of semiconductor devices, a structure in which a conductive material such as polycrystalline Si is buried in a contact hole to planarize an insulating film has come to be used (for example, Japanese Patent Application Laid-Open No. 1983-1999). 132
Publication No. 454).

FIG. 7 shows a conventional example of a MO5I-transistor having such a structure. In this conventional example, the insulation 11! is placed on the semiconductor substrate 11! i! Contact holes 14a and 14b reaching source/drain regions 13a and 13b are formed in the one-color edge film 12.

A conductive material 15 such as polycrystalline St is buried in the contact holes 14a and 14b, and Aβ wirings 16a and 16b are connected to this conductive material 15.

[Problem to be solved by the invention]

By the way, another Al wiring 17 not connected to this MO3+- transistor is also arranged on the semiconductor substrate 11.

As shown in FIG. 7, if the second wiring VA17 passes over the source/drain regions 13a, 13b, the contact holes 14a, 14b are moved to the left in FIG. It cannot be expanded further along this line.

As a result, the conductive material 15 and the source/drain region 13a,
The contact area with 13b is small, and the source/drain region 1
The contact resistance to 3a and 13b is large.

Conversely, contact holes 14a, 1 are formed in order to reduce the contact resistance to source/drain regions 13a, 13b.
4b along the gate electrode 18,
It is necessary to prevent the wiring 17 from passing over the source/drain regions 13a and 13b, which reduces the degree of freedom in arranging the wiring 17.

In other words, in the conventional example shown in FIG. 7, it is not possible to simultaneously reduce the contact resistance for the source/drain right page regions 13a and 13b and increase the degree of freedom in arranging the Al wiring 17.

[Means to solve the problem]

In the semiconductor device according to the present invention, an insulating film 12 is formed on a surface where regions 13a and 13b to be electrically connected are exposed and has openings 14a and 14b facing the regions 13a and 13b. , the first conductive material 15 buried in the openings 14a and 14b, and the opening 14a.
, 14b, respectively, are provided with second conductive materials 16a and 16b connected to the first conductive material 15 with an area smaller than that of the conductive materials 16a and 14b.

[Effect]

In the semiconductor device according to the present invention, the first conductive material 15 and the second conductive material
Compared to the contact area with the conductive materials 16a and 16b, the insulation 1
Since the areas of the openings 14a and 14b of 912 are larger, the contact area of the first conductive material 15 with the regions 13a and 13b to be electrically connected is larger.

Conversely, since the contact area between the first conductive material 15 and the second conductive material 16a, 16b is smaller than the area of the openings 14a, 14b of the insulating film 12, the opening 14a of the insulating film 12
, 14b may be provided with a conductive material 17 other than the second conductive materials 16a and 16b.

〔Example〕

Hereinafter, an embodiment of the present invention applied to a MO3I-transistor will be described with reference to FIGS. 1 to 6.

FIG. 1 shows this embodiment. In manufacturing this embodiment, steps up to the formation of the insulating film 12 are carried out in the same manner as in the conventional example described above.

Next, contact holes 14a and 14b are formed in the insulating film 12, but these contact holes 14a and 14b are
is formed to be expanded along the gate electrode 18 compared to the conventional example shown in FIG.

Next, a conductive material 15 such as polycrystalline Si is deposited on the entire surface of the semiconductor substrate 11 by CVD, and etch hacking is performed to fill the contact holes 14a and 14b with the conductive material 15. After that, if necessary, impurities are introduced into the conductive material 15.
reduce the resistance of

Next, another insulating film 21 is formed on the insulating film 12 and the conductive material 15 by CVD, oxidation, or the like.

Contact holes 22a, 2 are formed in this insulating film 21.
2b, these contact holes 22a,
The contact holes 22b are formed in substantially the same position and the same area as the contact holes 14a and 14b in the conventional example shown in FIG.

After that, Al vapor deposition and patterning are performed, and if wiring 16a, 16b, 1? form.

In this embodiment having the above configuration, the contact area between the conductive material 15 and the source/drain regions 13a, 13b is larger than that in the above-mentioned conventional example. Resistance is also small.

Furthermore, an insulating film 21 is formed on the conductive material 15, and the contact holes 22a and 22b formed in this absolutely 1i11!21 have approximately the same area as the contact holes 14a and 14b in the above-mentioned conventional example. So, ^l
The arrangement &117 can also be arranged in the same manner as in one conventional example.

Therefore, in this embodiment, the source/drain regions 13a,
It is possible to achieve both a reduction in contact resistance with respect to the Al wiring 13b and an increase in the degree of freedom in placement of the Al wiring 17.

By the way, when burying a conductive material in a contact hole,
First, as shown in FIG. 2A, the semiconductor substrate 11 and the insulating film 1 are
A conductive material 15 is deposited on the entire surface of the substrate 2, and then the conductive material 15 is etched back as shown in FIGS. 2B and 2C.

However, when the contact holes 23a and 23b have a square planar shape, and the length of one side of the contact hole 23b is less than twice the deposited thickness of the conductive material 15, as shown in FIGS. 2B and 2C. As shown in the figure, the contact hole 23b is completely filled with the conductive material 15, but the length of one side of the contact hole 23a is filled with the conductive material 15.
If the thickness of the contact hole 23a is more than twice the deposition thickness of
are not completely filled with the conductive material 15.

Therefore, when electrical connection is made to a large area, instead of forming a single contact hole with a large area like the contact hole 23a, a contact hole with a narrow area is formed as shown in FIG. A plurality of contact holes 23b are arranged in a mesh pattern, and electrical connection to a single region is made by the entirety of the plurality of contact holes 23b.

However, in the method shown in FIG. 3, since the regions between the contact holes 23b do not contribute to electrical connection, the contact resistance of the plurality of contact holes 23b as a whole is correspondingly large.

However, as shown in FIG. 4, if a contact hole 23C with a rectangular planar shape and a length of its short side equal to or less than twice the deposited thickness of the conductive material 15 is used, the length of the long side is the same as that of the conductive material 15.
This contact hole 23C is completely filled with the conductive material 15 even if the thickness is more than twice the deposition thickness of the conductive material 15.

Moreover, as shown in FIG. 4, a plurality of contact holes 23
If the contact holes 23b are arranged in a striped pattern, compared to the case where the plurality of contact holes 23b are arranged in a mesh pattern as shown in FIG.
Since the area between the contact holes 23c, that is, the area that does not contribute to electrical connection, is small, the contact resistance is also small.

Conversely, the entire area of the plurality of contact holes 23c is
If the same as in the case shown in the figure is acceptable, the area of the region in which the contact hole 23c is to be formed may be small as shown in FIG. 5, so that the MOS transistor or the like can be further miniaturized.

For this reason, in the present embodiment shown in FIG. 1, the planar shape of contact holes 14a and 14b is rectangular, and the length of the short side thereof is set to be less than twice the deposited thickness of conductive material 15.

If this is done, the contact hole 14 as in this embodiment.
Even if contact holes a and 14b are long along gate electrode 18, these contact holes 14a and 14b are completely filled with conductive material I5.

Note that in this embodiment, the source/drain regions 13a, 1
3b is elongated along the gate electrode 18, so there are only one contact hole 14a and one contact hole 14b. However, if the source/drain regions 13a and 13b were wider in the direction away from the gate electrode 18, the contact holes 14a and 14b could be made as shown in FIGS. 4 and 5. As shown, a plurality of contact holes 14a and 14bt may be formed.

Furthermore, although the case where the planar shape of the contact hole 23c is rectangular has been described in FIGS. As shown in FIG. 6, a contact hole 23d having an arbitrary planar shape can also be used.

〔Effect of the invention〕

In the semiconductor device according to the present invention, the contact area of the first conductive material with the region to be electrically connected is large, and a conductive material other than the second conductive material is disposed in the region above the opening of the insulating film. Therefore, it is possible to achieve both a reduction in contact resistance to a region to be electrically connected and an increase in the degree of freedom in arranging the conductive material on the insulating film.

15-- Conductive material 16a,
16b, 17--A Il wiring.

Claims (1)

[Scope of Claims] An insulating film formed on a surface where a region to be electrically connected is exposed and having an opening facing the region, and an insulating film buried in the opening. A semiconductor device comprising: a first conductive material; and a second conductive material connected to the first conductive material in an area smaller than the opening.