JPH0282579A - Manufacturing method of thin film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor applied to active matrix liquid crystal displays, image sensors, three-dimensional integrated circuits, and the like.

[Conventional technology]

Conventional thin film transistors are, for example, JAPANDISP
It had a structure as shown in LAY '86, 1986, pages 196-199. This structure is generalized and its outline is shown in Figure 2. (a) Figure is a top view, (b)
The figure is a cross-sectional view at AA'. A source electrode 202 and a drain electrode 203 are formed on an insulating substrate 201 made of glass, quartz, sapphire, etc., which are made of a polycrystalline silicon thin film doped with impurities to serve as donors or acceptors. A source electrode 204 and a drain electrode 205 are provided in contact with this, and a semiconductor layer 206 made of a polycrystalline silicon thin film is further formed in contact with the upper side of the source electrode 202 and the drain electrode 203 to connect them. A gate insulating film 207 is formed by thermal CVD to cover these. Furthermore, a gate electrode 208 is provided in contact with this.

[Problem to be solved by the invention]

However, conventional thin film transistors have the following problems.

The strength of the substrate is maintained at 400°C by thermal CVD method,
#7059 as a substrate to form a gate insulating film
(manufactured by Corning), the thermal expansion coefficient of the gate insulating film is as small as approximately 6xICM', whereas #705
Since the No. 9 substrate was as large as 46xlO-ma, warpage and deformation of the substrate after formation of the gate insulating film, cracking of the gate insulating film, etc. occurred, which caused defects in the thin film transistor. Furthermore, when the size of the substrate is increased, the above-mentioned phenomenon becomes noticeable, and the increase in size of the substrate is largely prevented.

Furthermore, when a gate insulating film is formed by thermal CVD, the quality of the formed insulating film is poor, and the surface charge density of the thin film transistor is as high as about I x 10"am-', which significantly reduces reliability.

In the thermal CVD method, the quality of the 5101 film adhering to the jig for setting the substrate or the chamber is poor, and it easily peels off, generating particles and causing pinholes in the formed gate insulating film, which can cause defects in thin film transistors. It had become.

The present invention is intended to solve these problems, and its purpose is to provide a highly reliable thin film transistor over a large area with fewer defects.

[Means to solve the problem]

The thin film transistor of the present invention is characterized in that the taper angle of the cross-sectional shape of the source electrode and the drain electrode is 60 degrees or less, and the gate insulating film is formed by the ECR plasma CVD method.

〔Example〕

The present invention will be described in detail below based on Examples.

FIG. 1 shows the structure of a thin film transistor according to the present invention.

As shown in FIG. 1(a), a silicon thin film of polycrystalline silicon, amorphous silicon, etc. doped with impurities to serve as donors or acceptors is deposited on an insulating substrate 101 made of glass, quartz, sapphire, etc. by low pressure CVD or plasma CVD. CV of law etc.
A photoresist film is formed in a predetermined shape using zero-order photolithography technology using the D method, vacuum evaporation method, or sputtering method, and the silicon thin film is etched using dry etching technology to form a source electrode 102 and a drain electrode 103. do. The gas used for etching was a mixed gas of CFa gas and 02 gas.
If the lOp ratio is decreased, the taper angle 104 is decreased, and conversely, if the CF al Oe ratio is increased, the taper angle 104 is decreased.
becomes larger. By strictly controlling the CF*10e ratio, the taper angle 104 can be adjusted with good reproducibility. C.F.
4102=0.25, and a taper angle 104 of 60 degrees was obtained. The film thickness of the source electrode 102 and the drain electrode 103 is preferably 500 to 5000 Å.

As shown in FIG. 1(b), source wiring 105 and drain wiring 106 made of metal, transparent conductive film, etc. are formed by sputtering or vacuum evaporation, and are made of silicon thin film such as polycrystalline silicon or amorphous silicon. semiconductor layer 1
07 is formed by a CVD method such as a low pressure CVD method or a plasma CVD method, or a vacuum evaporation method. The film thickness is 200O
Next, a gate insulating film 108 of 5ide, SiNx, etc. is formed by the ECR plasma CVD method, which is preferably less than A. The outline of the apparatus used is shown in Fig. 3.The main parts are a plasma chamber 303 and a sample chamber 310.
03 through the quartz window 311, the frequency is 2.45 GHz,
A microwave 307 of 1107-600 W can be supplied with a magnetic field by a magnetic coil 305 on the outer periphery. Highly active plasma and ion flow 304 generated by the interaction of microwaves and magnetic fields in the plasma chamber are transported to the sample chamber 310 by the divergent magnetic field, and a film is formed on the insulating substrate 301 through gas phase reaction and surface reaction. . When forming 5ins, 15*ccn of oxygen gas is supplied from the gas line 306 to the gas line 3.
From 08, 61 tell of 5iHn gas was supplied. The pressure at this time was 6.0xlO-'Torr, and the formation rate was about 670 A/min. Its film thickness is 10
The substrate 301 fixed on the sample stage 302, which is preferably 00 to 5000 A, can obtain a high-quality film at low temperature due to the impact effect of the highly active plasma and ion flow, while the ECR plasma CVD method has a strong directionality of the highly active plasma flow. Therefore, the fragility of the step side wall becomes remarkable. As a result, the breakdown voltage of the gate insulating film becomes extremely low. The relationship between the breakdown electric field strength and the taper angle is shown in Figure 5. This breakdown electric field strength is highly dependent on the taper angle; When it was set below, a large value of 6 MV/cm was obtained.

Finally, a gate electrode 109 made of metal or a transparent conductive film is formed by sputtering or vacuum evaporation.

In the thin film transistor configured in this manner, by setting the taper angle to 60 degrees or less, the breakdown voltage of the gate insulating film can be increased, and defects in the thin film transistor can be reduced.

In addition, since the gate insulating film can be formed without heating the substrate, if a glass substrate with a high thermal coefficient of 115 m is used as the substrate, the difference in thermal expansion coefficient between the formed gate insulating film and the glass substrate will be a problem. There is no warping or deformation of the substrate, cracking of the gate insulating film, etc.

In addition, since the reaction gas is efficiently decomposed and a film is formed, there is almost no film adhering to the walls of the sample chamber 310, and in principle, fewer particles are generated, making it easy to form a gate insulating film without pinholes. can be obtained.

Furthermore, before supplying the reaction gas, 5xlO-'Torr
The following high vacuum was applied, and the film formation was also carried out to -''r.

Since it is formed on an RR stage, there are extremely few impurities in the formed gate insulating film, and as a result, the surface charge density of the thin film transistor is 1/3 to 1/10 of the thermal CVD method, which greatly improves the reliability of the thin film transistor. can be improved.

The characteristics of the thin film transistor of the present invention are shown in FIG. 4, where the horizontal axis is the gate voltage vo· and the vertical axis is the logarithm of the drain current IQ. The drain voltage v■ is 4V, and both the channel length and channel width are 10 μm. The semiconductor layer is made of polycrystalline silicon and its thickness is 200 mm, and the gate insulating film is SiO.
2, the film thickness is 1500 people. The broken line represents a thin film transistor whose gate insulating film was formed by the conventional thermal CVD method, and the solid line represents a thin film transistor formed by the ECR plasma CVD method of the present invention. As is clear from FIG. 4, since the surface charge density has decreased, the drain current In at the gate voltage Ov has become smaller by about four orders of magnitude, and the rise in the subthreshold region has become steeper, improving the characteristics. As a result, when applied to a liquid crystal display, low-voltage driving becomes possible, and a high-quality display with a large contrast ratio can be realized.

When applied to image sensors and three-dimensional integrated circuits, low voltage drive and low power consumption can be achieved.

〔Effect of the invention〕

The present invention has the following excellent effects. First, the breakdown voltage of the gate insulating film of the thin film transistor increases, reducing defects and improving reliability.

Second, the difference in thermal expansion coefficient between the gate insulating film and the glass substrate does not become a problem, and there is no warping or deformation of the substrate, cracking of the gate insulating film, etc., and thin film transistors with few defects can be formed over a large area. can.

Third, the surface charge density of the thin film transistor is 1×10−
The distance is as small as 1°m-' to 3X10-"cm-", and reliability can be greatly improved.

Fourthly, the ECR plasma CVD method generates few particles in principle, and a gate insulating film without defects such as pinholes can be easily obtained, making it possible to reduce the number of defects in thin film transistors.

Fifth, the electrical characteristics of thin film transistors are improved, and a liquid crystal display that can be driven at low voltage and has a high contrast ratio can be realized.

As described above, the thin film transistor of the present invention has many excellent effects, and its application range is wide-ranging, including active matrix substrates for displays, peripheral circuits thereof, image sensors, and three-dimensional integrated circuits.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are cross-sectional views showing a method of manufacturing a thin film transistor of the present invention. FIGS. 2(a) and 2(b) show the structure of a conventional thin film transistor, in which a) is a top view and FIG. 2(b) is a cross-sectional view. FIG. 3 is a schematic diagram of an ECR plasma CVD apparatus. FIG. 4 is a graph showing the characteristics of thin film transistors. FIG. 5 is a graph showing the relationship between the breakdown electric field strength and the taper angle of the gate insulating film. 101.201,301...Insulating substrate 102.202
...Source electrode 103.203...Drain electrode 107.206...Semiconductor layer 105.204...Source wiring 106.205...Drain wiring 108.207...First insulating film 304...・Ion flow 109.208...Gate electrode 303...Plasma chamber 305...Magnetic coil 306.308...Gas line 307...Microwave 309...Evacuation 310...Sample chamber 311 ...quartz window

Claims (2)

[Claims] (1) A source electrode and a drain electrode, a semiconductor layer connecting the source electrode and the drain electrode, a gate insulating film covering the semiconductor layer, and a gate insulating film provided on a predetermined substrate. 1. A thin film transistor comprising a gate electrode, wherein the angle formed between the substrate surface and the etched surface of the cross-sectional shape of the source electrode and the drain electrode (hereinafter referred to as a taper angle) is 60 degrees or less. (2) The thin film transistor according to claim 1, wherein the gate insulating film is formed by an electron cyclotron resonance plasma CVD method (hereinafter referred to as ECR plasma CVD method).