JPH0283620A - Random number generation circuit - Google Patents

Abstract

PURPOSE:To take out a false random signal pattern equivalent to a signal when a circuit is operated by a fast clock signal by inputting the output of an exclusive OR circuit by feeding back to the input terminal of a forefront flip-flop, and taking out the false random signal from the output of an arbitrary flip-flop. CONSTITUTION:The (m) output terminals of the flip-flops 1-1 to 1-(n-1) are connected to the input terminals of the next flip-flops 1-2 to 1-n. Also, the output of (m) exclusive OR circuits 2-1 to 2-m receiving 2m output from the arbitrary flip-flops 1-1 to 1-1-n as pairs are fed back and inputted to the (m) input terminals of the forefront flip-flop 1-1. Therefore, the signal of (m) bits can be obtained simultaneously from each of the flip-flops 1-1 to 1-n at every clock. In such a way, it is possible to obtain a PN signal pattern (2<mn>-1) equivalent to the signal when being operated by the fast clock signal without setting the pattern of the PN signal at (2<mn>-1)/m even if a clock signal is m-frequency divided.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides a signal sequence having a sufficiently long period, and
The present invention relates to a random number generation circuit for generating a pseudorandom signal (also referred to as a PN signal) that can be considered to be generated independently without affecting each other and is used in place of a completely random signal.

Such a pseudorandom signal is used as a signal for measuring line quality of a digital transmission line, or as a test signal for a code error characteristic test, a jitter characteristic test, etc. of a digital repeater. In addition, in digital transmission, in order to prevent the clock component from disappearing due to transmission of a specific pattern, or to suppress the generation of discrete frequency components due to the periodicity of the transmitted pulse train, a scrambler is used to convert the input pulse train to a random pulse train. The maximum periodic sequence is also used for bra. Pseudo-random signals are also used in fault detection equipment and communication satellite telemeter signal synchronization.

[Prior Art] Generally, a maximum periodic sequence of pseudorandom signals is often used as a pseudorandom signal, but a random number generation circuit that generates this maximum periodic sequence of pseudorandom signals consists of several shift registers and a feedback logic circuit. It can be configured using

FIG. 3 is a circuit diagram showing a conventional random number generation circuit. In this FIG. 3, 5-1 to 5-4 are four cascade-connected 8-bit shift registers.
The output end of the final bit of each shift register 5-3 is connected to the input end of the next shift register 5-2 to 5-4. Also,
6 are the two output ends (28
, 31st) as a pair, and the output of this exclusive OR circuit 6 is fed back to the input terminal of the first shift register 5-1. It is now entered.

Here, 2, which is the two output ends of the shift register 5-4,
8. The exclusive OR of the signals from the 31st terminal is performed because this connection method provides the longest known PN signal (pseudorandom signal) pattern. Without being limited to this, the shift register 5-
You may take the exclusive OR of any two outputs from 1 to 5-4.

With this configuration, all shift registers 5-1
By operating 5-4 at the same time with a common clock signal, the random numbers represented by I O+ and 11' are shifted one after another, and the exclusive logic of the two signals reaching the output end of shift register 5-4 is Take the sum and shift register 5-
1. Return to This allows us to remove all zero sequences <(2"~1)
A pseudo-random pulse train signal or PN signal having a period of bits is obtained, for example, by extracting a signal to the input end of the shift register 5-1. Note that a PN signal can be obtained no matter which terminal from which the signal is taken out as shown in FIG.

[Problems to be Solved by the Invention] Normally, in a random number generation circuit, the tarot There is a limit to the clock signal period beyond which the signal interval can no longer be shortened. In other words, if the tarok signal is input to each device at a cycle shorter than the delay time, the next tarok signal will be input before the PN signal corresponding to a certain clock signal is output, making it difficult to perform accurate random number generation operation. I won't be able to do it.

On the other hand, in digital transmission systems, in recent years, as transmission speeds have increased, clock signals for operating circuits have also become faster. If a conventional random number generation circuit is used in such a high-speed digital transmission system, it may not operate accurately due to the above-mentioned clock signal period limit. Therefore, if a high-speed clock signal is frequency-divided and each device uses eight signals, the pattern of the PN signal inevitably decreases by the frequency division of the tarock signal. For example, in the circuit shown in Figure 3, if the clock signal is frequency-divided by 4 and input to each device, the pattern of the PN signal obtained during a certain period of time will be (231 to 1)/4. .

The present invention has been made in view of these problems, and even if the clock signal is frequency-divided and input to correspond to the high-speed clock signal, the i (Q random An object of the present invention is to provide a random number generation circuit that can obtain a signal pattern.

[Means to solve the problem] FIG. 1 is a circuit diagram of the principle of the present invention.

In Fig. 1, 1 to 1 to 1 to n are n m-bit flip-flops (CD flip-flops) connected in cascade, each having m input terminals (D terminal) and output terminals (Q terminal).
The m output terminals of the flip-flops 1-1-1-(n-1) are connected to the next flip-flops 1-1, respectively.
It is connected to the input terminals of 2 to 1 to n.

In addition, 2-1 to 2-m are arbitrary flip-flops 1 to 1
~1~n [In Figure 1, flip-flops 1~(n-1
), receives 2m outputs from 1 to n) in pairs m
Exclusive OR circuit.

The outputs of the m exclusive OR circuits 2-1 to 2-m are fed back and input to the m input terminals of the leading flip-flops 1 to 1, respectively.

[Function] With the above configuration, each flip-flop 1-1-1-n
A common clock signal is input to each flip-flop 1.
By operating ~1~1~n simultaneously, the signals to the input ends of flip-flops 1~1~1~(n-1) are transmitted from the output ends to the next flip-flops 1~2~l, respectively.
-n is output to the input terminal. In other words, the random numbers represented by '0' and '1' are shifted to the next flip-flop every 1 tarok at a pitch of 1 mm. Then, the signals reaching the output terminals of flip-flops 1 to (n-1) and 1 to n are paired and sent to an exclusive OR circuit 2-1.
~2-m, exclusive OR is taken, and the result is fed back to flip-flops 1-1.

As a result, the maximum (21nn-1) excluding all zero series
For example, as shown in FIG.
It is obtained by extracting the signal from the output terminal of flip-flop 1 to the input terminal of flip-flops 1 and 2. Note that a PN signal can be obtained no matter which terminal from which the signal is taken out as shown in FIG.

Furthermore, when a PN signal corresponding to a high-speed clock signal that exceeds the clock cycle limit due to the delay time of the device is required, the high-speed tallock signal is divided by m, for example, to obtain a tallock signal within the clock cycle limit. Then, this clock signal is applied to each flip-flop 1-1-1.
Commonly input to ~n. At this time, since m-bit signals are obtained simultaneously for each clock from each flip-flop 1 to 1 to L-n, even if the clock signal is divided by m,
The PN signal pattern is not (2IIn-1)7m, but the same PN as when operating with a high-speed clock signal.
A signal pattern (2111n 1) is obtained.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing a random number generation circuit as an embodiment of the present invention. As shown in FIG. 2, eight 4-bit flip-flops (D flip-flops) 3-1 to 3-3- 8
are connected in cascade, and the eight outputs from the flip-flops 3-7, 3-8 are connected in pairs to the four exclusive OR circuits 4.
-1 to 4-4 are input.

Here, each of the flip-flops 3-1 to 3-8 has four input terminals (D terminals) and an output terminal (Q terminal),
The four output terminals of the flip-flops 3-1 to 3-7 are connected to the input terminals of the next flip-flops 3-2 to 3-8, respectively.

Further, the exclusive OR circuit 4-1 includes a flip-flop 3
The exclusive OR circuit 4-2 receives signals from the 25th output terminal and 28th output terminal of the flip-flop 3-7 and the 26th output terminal of the flip-flop 3-7.
The exclusive OR circuit 4-3 receives the signal from the 29th output of the flip-flop 3-7 and the 30th output of the flip-flop 3-8. Furthermore, the exclusive OR circuit 4-4.

It receives a pair of signals from the 28th output terminal of flip-flop 3-7 and the 31st output terminal of flip-flop 3-8. The exclusive OR circuits 4-1 to 4-4 are connected as described above because, as mentioned above, this connection method provides the longest known PN signal pattern. However, the present invention is not limited to such a connection method.

The outputs of the four exclusive OR circuits 4-1 to 4-4 are fed back and input to the four input terminals of the leading flip-flop 3-1, respectively.

With the above configuration, each flip-flop 3-1 to 3-8
A common tarok signal is input to each flip-flop 3.
By operating -1 to 3-8 simultaneously, the signals to the input terminals of flip-flops 3-1 to 3-7 are transferred from the respective output terminals to the input terminals of the next flip-flops 3-2 to 3-8. Output. In other words, the random numbers represented by '0' and 11' are shifted to the next flip-flop in units of 4 bits every clock. The signals reaching the output terminals of the flip-flops 3-7 and 3-8 are then paired to exclusive OR circuits 4-1 to 4-4.
The signals are input to , exclusive ORed, and fed back to the four input terminals of the flip-flop 3-1, respectively.

As a result, in this embodiment, all zero sequences are excluded.

The l)N signal with a period of (231 to 1) bits can be obtained, for example, by extracting the signal from the output terminal of the Noritub flop 31 to the input terminal of the flip-flop 3-2, as shown in FIG. It will be done.

On the other hand, as clock signals have become faster due to high-speed transmission, when a PN signal corresponding to a clock signal that exceeds the clock period limit due to the delay time of each component device of the circuit is required, firstly, use the high-speed clock signal. For example, divide the frequency by 4. In this way, a clock signal within the clock cycle limit is obtained, and this tarlock signal is commonly input to each of the flip-flops 3-1 to 3-8.

At this time, in this embodiment, each flip-flop 3-1 to
Since a 4-bit signal is obtained from 3-8 at the same time, even if the clock signal is divided by 4, the PN signal pattern will be (2"-1)/as in the conventional circuit shown in Figure 3. 4
A PN signal pattern (231 to 1) equivalent to that obtained when operating with a high-speed clock signal that is not frequency-divided can be obtained.

In this way, according to the random number generation circuit of this embodiment.

Even if the clock signal speeds up, by dividing the clock signal and using it, you can obtain the same PN signal pattern as when operating with a high-speed clock signal without being affected by the delay time of each device. be.

In addition, in the above embodiment, exclusive OR circuits 4-1 to 4-
4 is connected to the output terminal of the flip-flop 3-7.3-8, and the PN signal is taken out from between the flip-flops 3-1.3-2, but the present invention is not limited to this. Instead, the exclusive OR circuits 4-1 to 4-4 may be connected to receive the outputs from arbitrary flip-flops 3-1 to 3-8 in pairs, and the PN signal may be can be obtained from the output terminals of flip-flops 3-1 to 3-8.

Further, in the above embodiment, a case has been described in which eight flip-flops and four exclusive OR circuits are provided, but the present invention is not limited to this.

[Effects of the Invention As detailed above, according to the random number generation circuit of the present invention,
n m-bit flip-flops are connected in cascade, and 1m exclusive OR circuits receive the outputs from arbitrary flip-flops in pairs, and the outputs of these m exclusive OR circuits are sent to m of the first flip-flop. Since the clock signal is fed back to each input terminal, and a pseudo (random signal) is extracted from the output of any flip-flop, even if the clock signal speeds up, by dividing the frequency of the clock signal, each It has the advantage of being able to extract a pseudorandom signal pattern equivalent to that obtained when operating with a high-speed clock signal without being affected by the delay time of the device.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the principle of the present invention, FIG. 2 is a circuit diagram showing a random number generation circuit as an embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional random number generation circuit. In the figure, 1-1-L-n are m-pitch 1-flip-flop, 2-1
~2-m is an exclusive OR circuit, 3-1~3-8 are 4-bit flip-flops, and 4-1~3-8 are 4-bit flip-flops.
4-4 is an exclusive OR circuit. Agent Patent Attorney Sada Igata −

Claims (1)

[Claims] n m-bit flip-flops (1-
1 to 1-n: 3-1 to 3-8) and m exclusive circuits that receive outputs from arbitrary flip-flops (1-1 to 1-n; 3-1 to 3-8) in pairs. OR circuit (2-1-2-
m; 4-l to 4-4), and the outputs of these m exclusive OR circuits (2-1 to 2-m; 4-1 to 4-4) are connected to the top flip-flop (1-l ;3-1) by feeding back and inputting them to the m input terminals of
A random number generation circuit that extracts a pseudorandom signal from the output of.