JPH0283631A - Memory access system for duplex information processor - Google Patents

Abstract

PURPOSE:To prevent performance from being lowered by providing a memory access space so that a memory content to be processed can be compared with that in a spare system by a program running on the processor of a processing system in a duplex information processor which sets the same memory content on both processing and spare systems. CONSTITUTION:The processing system 10 is equipped with the processor 1, a memory 2, a memory update means 3, and an input/output means 4, and the spare system 20 is equipped with the processor 5, a memory 6, a memory update means 7, and an input/output means 8. The processor 1 and the memory 2 in the processing system 10 execute the program to execute the processign of the input/output means 4. Simultaneously, a write order on the memory 2 is also sent to the memory 6 in the spare system 20 via the memory update means 3 and 7, which sets the same memory content on both systems 10 and 20. In such a way, it is possible to dispense with the synchronization of a clock level between both systems, and to easily check the memory content between both systems.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing device that is required to have high reliability.

(Prior Art) Conventionally, in this type of duplex information processing device, the same program is run in synchronization at the clock level in the processing system and the standby system, and the processing results of both systems are compared to guarantee the processing content. This guarantees that the data matches the contents of the memory of both systems.

In this type of redundant information processing equipment, when switching the system when a failure occurs in the processing system or periodically switching the system for preventive maintenance, the system can be switched instantly at the equipment level, and at the same time, In order to maintain continuity of processing, it is necessary to always match the memory contents of the processing system and the spare memory.

(Problem to be Solved by the Invention) In the conventional duplex processing device described above, in order to synchronize the processing of both systems at the clock level, the synchronization means limits the performance of the device and It has the disadvantage that it is difficult to measure the improvement in the processing capacity of the device, such as degrading the performance it already has.

An object of the present invention is to provide a duplex information processing apparatus in which the memory contents of both systems are the same, with a memory access space so that the processing memory contents and the memory contents of the standby system can be compared by a running program of the processor of the processing system. It is therefore an object of the present invention to provide a memory access method for a duplex information processing device configured to eliminate the above-mentioned drawbacks and prevent performance deterioration.

(Means for Solving Problem 1) The memory access method of the duplex information processing device according to the present invention consists of a processing system and a standby system, each of which is provided with a processor, memory, memory update means, and input/output means. .

In the above configuration, each processor is used to compare memory contents between its own system and other systems using a running program.

The memory update means is for executing a memory access operation in a two-system memory write mode, a self-system memory access mode, or an other-system memory access mode.

The memory has an address space corresponding to memory access operations by the memory update means.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory access method of a duplex information processing apparatus according to the present invention.

In FIG. 1, 1.5 is a processor, 2.6 is a memory, 3 and 7 are memory update means, and 4.8 is an input/output means. Also, 10
2 is a processing system, and 20 is a standby system.

The processing system 10 includes a processor 1, a memory 2, a memory update means 3, and an input/output means 4. The standby system 20 includes a processor 5, a memory 6, a memory update means 7, and an input/output means 8.

In the processing system 10, information processing is executed by a processor 1, a memory 2, and an input/output means 4.

FIG. 2 (C) is an explanatory diagram showing the operation mode of the memory update means 3.7 shown in FIG. 1. FIG. show,
(in FIG. 2) shows the access operation mode of the own system memory 2, and FIG. 2(C) shows the access operation mode of the other system memory 6.

In the saving operation mode of the memories 2 and 6 of both systems, the memory write order of the processing system 10 is converted to the memory write order of the standby system 20. In the access operation mode of the own system memory 2, the memory access order of the processing system 10 is not transmitted to the backup system 20. In the other system memory access mode, memory access from the processing system 10 to the standby system 20 is enabled.

FIG. 3 is an explanatory diagram showing an example of address space allocation for the access operation shown in FIG. 2.

In order to execute processing on the input/output means 4, the processing system 1
Processor 1 and memory 2 of 0 deepen the program. At the same time, the write order to the memory 2 is sent to the memory 6 of the standby system 20 via the memory update means 3 and 7, and the same contents are written to the memories 2 and 6. In this way, the memory contents of both systems 10 and 20 become the same.

In order to guarantee the identity of the memory contents of both systems 10 and 20, the processor 1 of the processing system 10 performs the process shown in FIGS. 2(b) and 2(C).
The contents of the processing system memory and the contents of the spare system memory are compared using the mode shown in . Naturally, the program that performs the above comparison is assigned to the lowest task so that it does not interfere with the execution of the tasks necessary for the service.

Here, if a queue for memory copy is provided in the memory update means 3 and 7, each system of the duplexing device can operate independently, which eliminates the need for the clock level (51st period) and enables high-speed operation. Become.

In the present invention, it is possible to check the identity of the memory contents of both systems 10 and 20 during program execution without providing any special hardware. Furthermore, by sequentially reading the memory contents of both systems 10 and 20, potential memory failures can be detected. Therefore, Mesori 2,6
By having an error correction function in the memory 2, it is possible to prevent software errors from accumulating in the memories 2 and 6 and falling into a state in which error correction is impossible.

(Effects of the Invention) As explained above, the present invention compares the processing system memory contents and the spare system memory contents using the running program of the processing system processor in a duplex information processing device in which the memory contents of both systems are made the same. By providing a memory access space so that it can be used, synchronization of clock levels between both systems is no longer necessary, and memory contents can be easily checked between both systems, and potential memory failures can be avoided. This has the effect of being able to detect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a memory access method of a duplex information processing apparatus according to the present invention. FIG. 2 is an explanatory diagram showing the access operation mode of the memory update means shown in FIG. 1. gg3 is an explanatory diagram showing an example of address space allocation for the access operation shown in FIG. 2. l, 5...Processor 2.6...Memory 3.7
...Memory update means 4.8...Input/output means 10...Processing system 20...
Preliminary Patent Applicant NEC Corporation Agent Patent Attorney Hisao Inoro Figure '2' 2 Ll Room 3]

Claims (1)

[Claims] processor, memory, memory update means,
and a memory access method for a redundant information processing device consisting of a processing system and a standby system provided with input/output means,
Each of the processors is for comparing memory contents between its own system and other systems by a running program, and
Each of the memory update means is for executing a memory access operation in a dual system memory write mode, own system memory access mode, or other system memory access mode; 1. A memory access method for a duplex information processing device, characterized in that it is configured to have an address space corresponding to an operation.