JPH02201656A - Checking system for duplex information processor - Google Patents

Checking system for duplex information processor

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Publication number
JPH02201656A
JPH02201656A JP2178389A JP2178389A JPH02201656A JP H02201656 A JPH02201656 A JP H02201656A JP 2178389 A JP2178389 A JP 2178389A JP 2178389 A JP2178389 A JP 2178389A JP H02201656 A JPH02201656 A JP H02201656A
Authority
JP
Japan
Prior art keywords
memory
processing system
contents
processing
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2178389A
Other languages
Japanese (ja)
Inventor
Yoshifumi Sasamoto
笹本 芳文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2178389A priority Critical patent/JPH02201656A/en
Publication of JPH02201656A publication Critical patent/JPH02201656A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To check contents correspondence by means of program running by providing a memory update mechanism, and comparing the memory contents of a processing system with the memory contents of an auxiliary system by means of the processor of the processing system. CONSTITUTION:Memory update mechanism 3 and 7 are provided with a function, which replaces the memory write order of a processing system 10 with the memory write order of an auxiliary system 11, a function, which does not transmit the memory access order of the processing system 10 to the auxiliary system 11 (a present-system memory access), and function, which attains the memory access of the auxiliary system from the processing system 10 (an another-system memory access). For the write order to a memory 2, the same contents are written through the memory update mechanism 3 and 7 to an auxiliary memory 6, and a processing system processor 1 compares the contents of the processing system memory 2 with the contents of the auxiliary system memory 6. A program to execute comparison is allocated to a low-order task, and the running of the task necessary for service is not prevented. Thus the processing ability of the device can be improved.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は二重化情報処理装置に関し、特に高信頼性を要
求される二重化情報処理装置のチエツク方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a duplex information processing apparatus, and particularly to a check method for a duplex information processing apparatus that requires high reliability.

[従来の技術] この種の二重化情報処理装置においては、処理系での障
害発生時の系切換え、又は予防保全のための定期的系切
換え時、装置レベルで瞬時に系切換えを行なうと同時に
、処理の連続性を保つために、処理系と予備系のメモリ
内容を常に一致させることが必要となる。
[Prior Art] In this type of redundant information processing equipment, when switching systems when a failure occurs in the processing system or periodically switching systems for preventive maintenance, system switching is performed instantaneously at the equipment level, and at the same time, In order to maintain continuity of processing, it is necessary to always match the memory contents of the processing system and the backup system.

従来、この種の二重化情報処理装置においては、処理系
と予備系とにおいて、同一のプログラムをクロックレベ
ルで同期させて走行し、両系の処理結果を比較して、処
理内容の保証と、両系メモリの内容一致の保証をしてい
た。
Conventionally, in this type of redundant information processing equipment, the same program is run synchronized at the clock level in the processing system and the standby system, and the processing results of both systems are compared to guarantee the processing contents and to The contents of system memory were guaranteed to match.

[発明が解決しようとする課題ゴ 上述した従来の二重化情報処理装置は、処理系及び予備
系の両系の処理をクロックレベルで同期させるために、
その同期機構が装置性能向上の妨げとなり、プロセッサ
、メモリの木来持っている性能を落してしまう等、装置
の処理能力の向上を計り難いという欠点があった。
[Problems to be Solved by the Invention] The conventional redundant information processing device described above has two methods:
The synchronization mechanism obstructs improvements in device performance, resulting in a drop in the performance of the processor and memory, making it difficult to measure improvements in the device's processing power.

[課題を解決するための手段] 本発明は、」−記課題を解決するためになしたもので、
その解決手段として本発明は、処理系と予備系とからな
り、これら処理系及び予備系の各々にプロセッサとメモ
リを有する二重化情報処理装置において、」−記処理系
のメモリ書込時に同時に予備系のメモリに同一内容を書
込むメモリアップデート機構を持ち、上記処理及び予備
両系のメモリ内容の同一性を保証するため、上記処理系
のプロセッサにより処理系のメモリ内容と予備系のメモ
リ内容を比較する構成としている。
[Means for Solving the Problems] The present invention has been made to solve the problems listed below.
As a means of solving this problem, the present invention provides a duplex information processing device consisting of a processing system and a standby system, each of which has a processor and a memory. It has a memory update mechanism that writes the same contents to the memory of the processing system, and in order to guarantee the sameness of the memory contents of both the processing system and the backup system, the processor of the processing system compares the memory contents of the processing system and the memory contents of the backup system. It is configured to do this.

[実施例] 次に、本発明の実施例について図面を参照して説明する
[Example] Next, an example of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示すブロック図、第2図(
a) (b) (C)は第1図の動作説明図で、(a)
は両系メモリライト時、(b)は自系メモリアクセス時
、(c)は他系メモリアクセス時を示すものである。
FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
a) (b) (C) is an explanatory diagram of the operation in Fig. 1; (a)
(b) shows the memory access of the own system, and (c) shows the memory access of the other system.

■、5はプロセッサ、2,6はメモリ、3゜7はメモリ
アップデート機構、4,8は入出力機構である。1,2
,3.4を処理系10.5゜6.7.8を予備系11と
して構成しである。
2 and 5 are processors, 2 and 6 are memories, 3.7 are memory update mechanisms, and 4 and 8 are input/output mechanisms. 1,2
, 3.4 as a processing system 10.5 degrees, and 6.7.8 as a backup system 11.

以下、動作の説明をする。The operation will be explained below.

処理系10のプロセッサ1.メモリ2及び入出力機構4
を用いて情報処理が実行される。
Processor 1 of processing system 10. Memory 2 and input/output mechanism 4
Information processing is performed using

メモリアップデート機構3,7は以下の機能を持つ。The memory update mechanisms 3 and 7 have the following functions.

(1)処理系のメモリライ)・オーダを予備系のメモリ
ライトオーダに変換する機能(第2図(a)両系メモリ
ライl−)。
(1) Processing system memory write order) - Function to convert the processing system memory write order into a spare system memory write order (FIG. 2(a) both system memory write order l-).

(2)処理系のメモリアクセスオーダを予備系に伝達し
ない機能(第2図(b)自系メモリアクセス)。
(2) A function that does not transmit the processing system's memory access order to the backup system (FIG. 2(b) Self-system memory access).

(3)処理系から予備系のメモリアクセスを可能とする
機能(第2図(C)他系メモリアクセス)。
(3) A function that enables the processing system to access the memory of the standby system (FIG. 2 (C) memory access of other systems).

ここで、第2図で示した機構を実現するためには、第2
図(a) (b) (c)を認識する信号線が準備され
る。通常、その信号はアドレス空間を分割する信号であ
る。
Here, in order to realize the mechanism shown in Fig. 2, the second
A signal line for recognizing the signals shown in FIGS. (a), (b), and (c) is prepared. Typically, the signal is one that divides the address space.

入出力機構4,8に対して処理を行なうために処理系プ
ロセッサ1及びメモリ2はプログラムを実行する。それ
と同時にメモリ2へのライトオーダはメモリアップデー
ト機構3,7を経由して予備系メモリ6に同一内容が書
込まれる。こうして、両系のメモリ内容が同一・となる
The processing system processor 1 and memory 2 execute programs to perform processing on the input/output mechanisms 4 and 8. At the same time, the same contents of the write order to the memory 2 are written to the spare memory 6 via the memory update mechanisms 3 and 7. In this way, the memory contents of both systems become the same.

両系10,11のメモリ内容の同一性を保証するために
、処理系プロセッサ1は第2図(b) Gc)で示した
機能を用いて処理系メモリ2の内容と予備系メモリ6の
内容を比較する。
In order to guarantee the identity of the memory contents of both systems 10 and 11, the processing system processor 1 uses the function shown in FIG. Compare.

当然、前記比較を実行するプログラムは最ド位タスクに
開封けられ、サービスに必要なタスクの走行を妨げない
ようになされる。
Naturally, the program that performs the comparison is opened to the lowest task so as not to interfere with the execution of the tasks necessary for the service.

[発明の効果] 以」−説明したように本発明の二重化情報処理装置のチ
エツク方式は、処理系と予備系とからなり、これら処理
系及び予備系の各々にプロセッサとメモリを有する二重
化情報処理装置において、上記処理系のメモリ書込時に
同時に予備系のメモリに同一内容を書込むメモリアップ
デート機構を持ち、」−記処理及び予備両系のメモリ内
容の同一性を保証するため、上記処理系のプロセッサに
より処理系のメモリ内容と予備系のメモリ内容を比較す
る構成としたため、以下の効果が生まれる。
[Effects of the Invention] As explained above, the check system of the duplex information processing apparatus of the present invention consists of a processing system and a standby system, and each of the processing system and standby system has a processor and a memory. The device has a memory update mechanism that simultaneously writes the same content to the memory of the standby system when writing to the memory of the processing system, and in order to guarantee the identity of the memory contents of both the processing and standby systems, the processing system Since the processor is configured to compare the memory contents of the processing system and the memory contents of the standby system, the following effects are produced.

(1)メモリアップデート機構にメモリコピーのための
待ち行列を設けると、二重化情報処理装置の各県の動作
が独立に実行でき、高速な動作が可能となる。即ち、従
来に比しクロックレベルの両系同期が不要となる。
(1) When a queue for memory copying is provided in the memory update mechanism, each prefecture of the duplex information processing device can perform operations independently, allowing high-speed operation. That is, compared to the prior art, there is no need to synchronize the clock levels of both systems.

(2)両系メモリの内容同一性チーツクを特殊なハード
ウェアを設けなくても、プログラム走行で実行できる。
(2) Checking the content identity of both memory systems can be executed by running a program without installing special hardware.

(3)両系のメモリを順次読出すことにより、潜在的メ
モリ障害を検出できる。このことはメモリにエラー訂正
機能を持てば、メモリのンフトエラーの蓄積でエラー訂
正不能状態に陥るのも防止できる。
(3) Potential memory failures can be detected by sequentially reading the memories of both systems. If the memory has an error correction function, it is possible to prevent the memory from becoming incapable of error correction due to accumulation of soft errors.

【図面の簡単な説明】 第1図は本発明の一実施例を示すブロック図、第2図(
a)(b)(c)は第1図の動作説明図で、(a)は両
系メモリライト時、(b)は自系メモリアクセス時、(
C)は他系メモリアクセス時を示すものである。 l、5:ブロセッザ 2.6:メモリ 3.7:メモリアップデート機構 4.8:入出力機構
[Brief Description of the Drawings] Figure 1 is a block diagram showing one embodiment of the present invention, and Figure 2 (
a), (b), and (c) are explanatory diagrams of the operation in Figure 1, where (a) is when writing to memory in both systems, (b) is when accessing memory in own system, and (
C) shows the time of accessing the memory of another system. l, 5: Brosseza 2.6: Memory 3.7: Memory update mechanism 4.8: Input/output mechanism

Claims (1)

【特許請求の範囲】[Claims] 処理系と予備系とからなり、これら処理系及び予備系の
各々にプロセッサとメモリを有する二重化情報処理装置
において、上記処理系のメモリ書込時に同時に予備系の
メモリに同一内容を書込むメモリアップデート機構を持
ち、上記処理及び予備両系のメモリ内容の同一性を保証
するため、上記処理系のプロセッサにより処理系のメモ
リ内容と予備系のメモリ内容を比較することを特徴とす
る二重化情報処理装置のチェック方式。
In a duplex information processing device consisting of a processing system and a backup system, each of which has a processor and a memory, a memory update in which the same content is written to the memory of the backup system at the same time as the processing system writes to the memory. A redundant information processing device characterized in that the processor of the processing system compares the memory contents of the processing system and the memory contents of the backup system in order to guarantee the sameness of the memory contents of both the processing system and the backup system. check method.
JP2178389A 1989-01-31 1989-01-31 Checking system for duplex information processor Pending JPH02201656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2178389A JPH02201656A (en) 1989-01-31 1989-01-31 Checking system for duplex information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2178389A JPH02201656A (en) 1989-01-31 1989-01-31 Checking system for duplex information processor

Publications (1)

Publication Number Publication Date
JPH02201656A true JPH02201656A (en) 1990-08-09

Family

ID=12064662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2178389A Pending JPH02201656A (en) 1989-01-31 1989-01-31 Checking system for duplex information processor

Country Status (1)

Country Link
JP (1) JPH02201656A (en)

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