JPH0283632A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To reduce man-hours required for the development of an emulation chip by incorporating a CPU and every kind of peripheral device, performing the input/ output of data with the peripheral device outside the emulation chip, and providing a function to switch an interruption request signal outputted from an unrequired peripheral device and that from the peripheral device outside the emulation chip. CONSTITUTION:The emulation chip 100 includes the CPU 101 which performs a data processing under the control of a program and the peripheral devices SFRA 102 and SFRB 103 such as a timer counter, a serial interface, etc., an interface circuit SFRIF 105 between the emulation chip 100 and the peripheral device outside the chip, and an interruption request switching circuit 106, and they are connected mutually with an SFR bus 107. The interruption request signal outputted from the peripheral device or an external input signal is selected corresponding to the value of a peripheral selection signal, and it is outputted to the CPU 101, then, data transfer between the peripheral device outside a single chip microcomputer and the CPU 101 is performed under the control of a selection discrimination signal. In such a way, it is possible to reduce human resources or an economical load consumed in the development of the emulation chip.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program development chip for developing a program to be executed on a single-chip microcomputer incorporating various peripheral hardware.

[Conventional example]

In recent years, as the range of applications for single-chip microcomputers has expanded, single-chip microcomputers adapted to various application fields have been developed.

In general, when developing a program that runs on a single-chip microcomputer, it is necessary to ensure that the execution operations of the program can be performed in the same way as on a single-chip microcomputer, and to confirm that the program is running according to a predetermined flow. A program development support tool (hereinafter referred to as IE) that has functions that facilitate program depacking, such as a function to interrupt program execution at a specific address (hereinafter referred to as break function), and a function to read and change the memory contents at that time. ) is used. In order to realize such functions on IE, a single-chip microcomputer (hereinafter referred to as Evachip external) for program development is added to the functions of a normal single-chip microcomputer with functions for IE such as internal status output. ) is used.

A single-chip microcomputer consists of a CPU that processes data based on the control of a program, and peripheral devices such as a timer counter, an A/D converter, and a serial interface. It is determined by the types and functions of peripheral devices built into the computer.

For this reason, products for each application field are often developed by developing single-chip microcomputers that use the same CPU and change peripheral devices to those optimal for each application field.

As a result, when developing single-chip microcomputers for each application field, it is necessary to develop corresponding EV chips individually, even though only the peripheral devices are different.

[Problem to be solved by the invention]

As mentioned above, even if the CPU is the same and only the peripheral functions are different, if a single-chip microcomputer optimal for each application field is independently developed, it is necessary to develop a corresponding EV chip. However, the disadvantage is that the human resources and economic burden required for development are large.

[Means to solve the problem]

The single-chip microcomputer according to the present invention includes:
A CPU and multiple peripheral devices are integrated on a single semiconductor substrate, and each of the multiple peripheral devices has a peripheral selection signal.
Peripheral selection means controls write/read processing by the CPU and outputs a selection determination signal according to the value of the peripheral selection signal, and selects an interrupt request signal and an external input signal output by the peripheral device according to the value of the peripheral selection signal. It is characterized by having a signal selection means for outputting to the CPU, and an input/output means for transferring data between the CPU and a peripheral device external to the single-chip microcomputer under the control of a selection determination signal.

In other words, the EV chip based on the present invention has a built-in CPU and various peripheral devices, has the function of inputting and outputting data with peripheral devices outside the EV chip, and also selects only the necessary peripheral devices using the peripheral selection signal. It has a function of switching an interrupt request signal output from a peripheral device that is not connected to an interrupt request signal from a peripheral device external to the evaluation chip.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The Evachip 100 consists of a CPU 10I that processes data based on program control, and 5FRAIO which is a peripheral device such as a timer counter and a serial interface.
2,5FRBI O3 and 5FRI which is an interface circuit between the Evachip 100 and peripheral devices outside the chip.
F105, interrupt request switching circuit (hereinafter referred to as INTSEL)
It is written as ) 106, CPU 101.5FRA1
The 02°5FRB 103 and 5FRIF 105 are interconnected by an SFR bus 107.

$FR engineering F105 has FRD signal 110 on the outside of the chip,
FWR signal 111. Outputs the FALE signal 112 and
Data is input/output to and from external peripheral devices via the D bus 108.

From CPU 101, peripheral device 5FRAI O2゜5F
5FRRD signal line 1 as read control signal to RE103
13. 5FRWR signal line 114 as a write control signal,
and a 5FRALE signal 115 that specifies the latch timing of address information on the SFR bus 107.

5FRAI02 and 5FRBIO3 send a selection determination signal 11 to 5FRIF105 indicating whether or not they are selected.
6,117 and for INTSEL106,
Interrupt request signals 118 and 119 (hereinafter referred to as
INTA respectively.

It is written as IN TB. ) is output.

In addition, an interrupt request signal 1 is sent from outside the evaluation chip 100.
20, 1.21 (hereinafter referred to as EINTA).

It is written as EINTB. ) to INTSEL106, peripheral selection signals 122, 123 to 5FRAIQ2゜5FRB10
3 is input to INTSEL106.

Also, INTSELl 06 has the following for CPUl0I:
Interrupt request signals 124, 125 (hereinafter referred to as engineering N)
They are written as TRQA and INTRQB. ) is output.

Next, detailed configurations of the peripheral devices 5FRAIO2 and 5FRB103 will be explained. Since 5FRA102 and 5FRB103 have similar configurations, here we will use 5FRA102 as an example to explain the second
This will be explained using figures.

The address discrimination circuit 130 compares the peripheral address information output on the SFR bus 107 with its own preset address value, and if they match, it sets it to 1, otherwise it sets it to O. Output to.

In the first AND gate 131, the address discrimination circuit 13
0 and the peripheral selection signal 122,
When the peripheral selection signal 122 is active (l), the output of the address discrimination circuit 130 is enabled, and the peripheral selection signal 1
When 22 is O, it always outputs O regardless of the output of the address discrimination circuit 130.

The address latch 132 captures and holds the output of the first AND gate 131 in synchronization with the 5FRALE signal 115. The output of the address latch 132 is output to the 5FRIF 105 as a selection determination signal 116.

Second AND gate 133. Third AND gate 134
are the outputs of the address latch 132, respectively SF1'lD
If the signals 113 and 5FRWR signals 114 are selected and the address latch 132 is active, 5F is selected, respectively.
RRD signal 113°5 FRWR signal 114 is enabled.

As a result, when the peripheral selection signal 122 is O, the output of the address latch 132 is always 0, and the output of the second AND gate 133. The third AND gate 134 outputs the 5FRRD signal 1
13,5FRWR signal 114 is not selected, and access by CPU 101 to 5FRA is disabled.

Next, the detailed configuration of the 5FRIF 105 will be explained using FIG.

Selection determination signals 116 and 117 output from 5FRA 102 and 5FRB 103 are input to NOR gate 140. The output is the fourth. Fifth. 6th AND gate 1
41, 142, 143 and FRD signals 110, F
Controls the WR signal 111 and FALE signal 112.

Further, the FRD signal 110, which is the output of the fourth AND gate 141, is transmitted to the output driver 144. Input driver 145
When the FRD signal 110 is '1'', the input driver 145 enters the ○N state, takes in the data on the FAD bus 108 onto the SFR bus 107, and outputs the FRD signal 11
When 0 is ++ O++, the output driver 144 is turned on and the data on the SFR bus 107 is transferred to the SAD bus 10.
Output to 8.

As a result, when the selection determination signals 116 and 117 are both 0, the 5FRIF 105 performs data transfer processing with the outside of the Eva chip 100 when the CPU 10I accesses data to the peripheral device.

Next, the detailed configuration of the INTSEL 106 will be explained using FIG. 4.

INTSELI 06 is 5ELAI 50,5ELB
Consists of 151.

The 5ELA 150 selects the INTA 118 when the peripheral selection signal 122 is '1''' and selects the EINTA 120 when it is 'llo', and outputs it as INTRQAl 24.

The 5ELB 151 selects the INTB 119 when the peripheral selection signal 123 is '1'''', and selects the EINTB 121 when it is '0'', and outputs it as INTRQEl 25.

FIG. 5 shows an example of the configuration of a system when emulation is performed using the evaluation chip 100 according to the present invention.

Peripheral chip 5FRC160 is Eva chip 1o.

Built-in peripheral devices 5FRAI O2, 5FRB 10
It is an integrated circuit that has built-in peripheral devices with functions different from that of 3. 5FRC160 has FAD bus 108°FRD signal 110. FWR signal 111. It is connected to the evaluation chip 100 via a FALE signal 112.

Further, the interrupt request signal output from the 5FRC 160 is connected to the EINTB signal 121 of the Eva chip 100.

Next, using the Eva chip of this embodiment, the peripheral device 5FR
The operation will be described when emulating a single-chip microcomputer in which the peripheral device A102 and the peripheral chip 5FRC160 are built in, but the peripheral device 5FRB103 is not built in.

In FIG. 5, "1" is input to the peripheral selection signal 122 and "0°' is input to the peripheral selection signal 123.

Since the peripheral selection signal 123 is "0", the first AND gate 131 in the 5FRB 103 is always 0 regardless of the output of the address discrimination circuit 130. For this reason, C
When PUl0I performs data access to 5FRB, both selection determination signals 116 and 117 become 0, and 5FRIF 105 accesses 5FRB via FAD bus 108.
Transfer data to FR0160. Also, INTS
EL106 is the INTAI output from 5FRA102.
Select EINTB121 connected to 1B and 5FRC160 and output to CPU10I. As a result, the fifth
The system shown in the figure can perform the same operation as a single-chip microcomputer with 5 FRAI O1 and peripheral devices 5 FRC.

By using the Eva-chip having the above-described configuration, manipulating the peripheral selection signal, and connecting a new peripheral device outside the Eva-chip, it becomes possible to emulate a new single-chip microcomputer.

Next, another embodiment of the present invention will be described with reference to FIG.

In the previous embodiment, the selection signal to the peripheral device was inputted from outside the EV chip, but in this embodiment, a mode register for selecting the peripheral device is built into the EV chip.

FIG. 6 is a block diagram of the Eva chip based on this embodiment. The evaluation chip 200 receives peripheral selection signals 222 and 223.
The configuration is the same as that of the first embodiment shown in FIG. 1, except that instead of being input from outside the EV chip, it is output from the mode register 226 inside the EV chip 200.

The mode register 226 is connected to the SFR bus 107, and the 5FRWR signal line 114 and FRFLE signal 115 are input from the CPU10I.
By writing from Ul0I, the peripheral selection signal 222
, 223.

As a result, by setting the mode register 226 with a command when starting up the EV chip, the values of the peripheral selection signals 222 and 223 are controlled, and as a result, the necessary peripheral devices are selected and the emulation is performed on the EV chip externally. By connecting the peripheral devices that are insufficient to perform this, it is possible to emulate a single-chip microcomputer that differs only in the peripheral devices, similar to the first embodiment.

〔Effect of the invention〕

As described above, by using the evaluation chip based on the present invention, even for a single-chip microcomputer with different peripheral devices, it is possible to create an emulation module by simply developing a new chip that includes only the peripheral devices that are not built into the evaluation chip. Since this is possible, the development man-hours and development costs required for the development of the EV chip can be reduced to the minimum.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram of peripheral devices, and Fig. 3 is a 5FR shown in Fig. 1.
IF block diagram, Figure 4 is the INTSE shown in Figure 1.
FIG. 5 is a block diagram showing an example of a system configuration using an EVA chip based on the present invention, and FIG. 6 is a block diagram showing another embodiment of the present invention. 100...Evachip, 101...C
PU1102...5FRA, 103...
・5FRB, 105...5FRIF, 1
06...INTSEL, 107...
・SFR bus, 108...PAD bus, 110
...FRD signal, 111...FWR signal, 112...FALE signal, 113...
...5FRRD signal line, 114...5FRWR
Signal line, 115...5FRALE signal, 116
, 117... Selection determination signal, 118...
INTA, 1 19...INTB, 12
0...EINTA, 121...EIN
TB, 122, 123... Peripheral selection signal, 12
4...INTRQA, 125...INT
RQBl 130...Address discrimination circuit, 13
1...First AND gate, 132...
・Address latch, 133...second AND gate), 134...third AND gate, 140
...NOR gate, 141...Fourth AND gate, 142...Fifth AND gate, 143...Sixth AND gate, 144...・
...Output driver, 145...Input driver, 150...5ELA, 151...
5ELB. 160...5FRC1200...Eva chip, 222.223...Peripheral selection signal, mode register.

Claims (1)

[Claims] In a single-chip microcomputer in which a CPU and a plurality of peripheral devices are integrated on a single semiconductor substrate, a selection determination signal is provided that controls write/read processing of the plurality of peripheral devices by the CPU according to the value of a peripheral selection signal. peripheral selection means for outputting a peripheral selection signal; signal selection means for selecting an interrupt request signal and an external input signal output by the peripheral device according to the value of the peripheral selection signal and outputting the selected signals to the CPU; and controlling the selection determination signal. External peripherals and the CPU
What is claimed is: 1. A single-chip microcomputer comprising input/output means for transferring data between the computers.