JPH0283679A - Data reader for optical card - Google Patents

Abstract

PURPOSE:To accurately obtain a data clock by providing a reference line detecting part to output the mean position signal of a reference line, and a data clock generating part to generate the data clock which becomes reference at the time of reading a data bit based on the mean position signal of the reference line. CONSTITUTION:The reference line detecting part 15 outputs mean position information from the read signal of the reference line, and the data clock generating part 16 generates the data clock which becomes reference at the time of reading the data bit based on the position information of the reference line. The data clock can be obtained by performing the 1/N-frequency division of a clock from an oscillation circuit 31 by synchronizing with the output of the mean position information from the reference line detecting part 15. A pulse is outputted at a position equivalent to the distance of the reference line of the data clock setting a mean position as reference. Then, the timing of the detecting signal of the reference line is compared with that of the pulse at a timing comparation circuit 34, and the output of the comparator is integrated, and is fed back to the oscillation circuit 31, then, a frequency is set. In such a way, an accurate data clock can be generated.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a data processing system that is formed by arranging a plurality of data tracks each consisting of a plurality of data bits in parallel along a reference line extending perpendicularly to the data track. The present invention relates to an optical card data reading device for reading an optical card having an area.

[Prior Art] As shown in FIG. 8, in the data recording area 2 of the optical card 1, data tracks 4, which are rows of data bits 3, are arranged vertically to form one band 5. A large number of such bands 5 are arranged in parallel. On the left side of the band 5 in the figure, two reference lines 6a are provided which serve as J3i directrix for detecting data bit 3. Also, 6b in the figure
is the reference line for band 5 in the next stage.

Data reading from such an optical card 1 is performed by the ninth
As shown in the figure and FIG. 10, the data light 8, for example, infrared light, is converged from the LED 7 and irradiated onto the optical card l, and the reflected light 9 is received by an image sensor such as a CCD line sensor lO. The data bits formed on the surface of the CPU 1 are sent to the CPU 12 via the decoder 11.
This is done by reading with 2.

From the CCD line sensor lO, the pickpocket 7 shown in Fig.
) 13, and this slit 13
The read signal shown in FIG. 8 is obtained by scanning the portion from left to right in the figure, and data 110 is identified by checking the presence or absence of data bit 3 from this read signal.

Specifically, data reading is performed using one data trunk 4.
is repeatedly scanned a plurality of times, and for each scan, a binary signal is read using the detection signal of the reference line 6a as a reference. Therefore, in order to accurately read the data recorded on the optical card l, the data track 4 that serves as a reference is required.
It is necessary to stably detect the reference line 6a and accurately synchronize with the data clock. Various methods have been proposed for this purpose, and PLL technology has been mainly used.

[Problems to be Solved by the Invention] However, conventional data reading devices have the disadvantage that when separating data using a data clock, it is necessary to adjust the magnification of the optical system in order to synchronize with the data clock. there were.

Furthermore, when extracting a booter long component from a read signal using a PLL, the read signal is divided by the scanning period of the sensor, and the phases are not continuous. Therefore, it is necessary to provide a synchronization bit for resynchronizing the data clock for each scan, and there is a problem in that if one bit is provided for each scan, the recording capacity of the optical card I will be reduced.

For example, when reading data based on the detection signal of the reference line 6a, if the reference line 6a is defective or dirty, an accurate detection signal or no detection signal may be obtained. This caused a problem in that an accurate data clock could not be obtained and data bits could not be read at all times.

[Means for Solving the Problems] - An optical card data reading device according to the present invention which solves the conventional problems described above reads a data track consisting of a plurality of data bits by a standard extending in a direction orthogonal to the data track. In an optical card data reading device that reads an optical card having a plurality of data slices arranged in parallel along a line, 1- a reference line that outputs average position information of the reference line from a read signal of the enlarged directrix; a detection section; and a data clock generation section that generates a data clock that is a reference when reading the data bits based on the average position information of the reference line, and the L hypertrophic directrix detection section is configured to detect the reference line based on the average position information of the reference line. a reference line detection circuit that detects the tI line and outputs a detection signal; an output circuit that produces an output indicating average position information of the reference line based on the detection signal from the reference line detection circuit;
Consisting of a timing comparison circuit that inputs the output of the hypertrophic directrix detection circuit and the output of the output circuit and compares the timing of both outputs, and an integration circuit that integrates the output of the timing comparison circuit and outputs it to the output circuit. - The data clock generation section inputs an oscillation circuit that outputs a clock having a frequency N times (N = integer) of the data clock to be generated, and the average position information output from the reference line detection section, and receives the average position information output from the reference line detection section. Synchronize with the output - clock from the oscillator circuit by 1/N
A frequency dividing circuit that divides the frequency into a data clock, and a frequency dividing circuit that divides the frequency into a data clock. A pulse generation circuit that outputs the pulse first at a position corresponding to the distance between the F lines, a timing comparison circuit that compares the timing of the detection signal of the reference line adjacent to the L hypertrophic directrix and the pulse, and the output of the timing comparison circuit. and an integrating circuit that integrates and sets the feedback 17 frequency in the oscillation circuit.

[Example] An example of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The data reading device according to this embodiment includes a reference line detection section 15 and a data crotter generation section 16. As shown in FIG.

The reference line detection section 15 outputs the reference line 6acy) average position information from the read signal of the reference line 6a, and includes a reference line detection circuit 20, a timing comparison circuit 21, an integration circuit 22,
It consists of a pulse generator 23.

The reference line detection circuit 20 detects a reference line 6a formed by two lines with a wider interval than the interval between the three data bits of the optical card 1 shown in FIG.
It is detected from the read signal of the D image 7/S 10 and outputs the detected pulse to the timing comparison circuit 21.

The distance between the two lines constituting the reference line 6a is
In the example shown in FIG. 8, the interval is 1.5 times the interval between data bits 3, and the reference line detection circuit 20 uses this interval difference to detect data bits from data bit 3 to reference line 6.
a is identified and detected.

The pulse generator 23 generates an output pulse after a preset time has elapsed from the timing of the synchronization signal synchronized with the scanning synchronization pulse of the CCD image sensor 10 .

Note that the read signal is changed little by little by the scanner multiple times for each data track 4, and does not change abruptly. Therefore, the temporal distance between the part of the read signal representing the reference line 6a and the synchronization signal also changes suddenly. There's nothing to do.

The timing comparison circuit 21 inputs the detection pulse of the reference line 6a and the feed-punked output pulse from the pulse generator 23, detects the Fi+- delay of both pulses, and generates a comparison output. This comparison output may be a digital one indicating whether one pulse is delayed or too early, or an analog output indicating how late or how early one pulse is. Although a combination of a pair of flip-flops 24 as shown in the figure can be used, the present invention is not limited to this, and various comparison circuits can be used.

The integrating circuit 22 is constituted by an up/down counter, and is turned up/down by the early/late pulses of the timing comparison circuit 21, and the pulse generator 23 is set by its output.

Next, the operation of the reference line detection section 15 configured as described above will be explained using the time chart of FIG. 2.

Here, for ease of understanding, the comparison output of the timing comparison circuit 21 is shown when the output pulse of the pulse generator 23 is too early and when the output pulse is too late.

If the comparison output of the timing comparison circuit 21 is "r early", the integration circuit 22 increases the value of the comparison output, and if it is "slow", the integration is performed by reducing the value of the comparison output.

The pulse generator 23 receives the output of the integrating circuit 22 and changes the time interval from the synchronization signal to the output according to the output. In addition, the output of the pulse generator 23 is returned to the timing comparison circuit 21, and the timing comparison circuit 21 compares 0 or more over multiple scans. The outputs of the reference line detection circuit 20 and the pulse generator 23 are controlled to have the same timing, and the positional information of the reference line 6a is averaged. Therefore, a stable detection result of the reference line 6a can be obtained.

For example, even if an abnormality occurs in the output of the reference line detection circuit 20 due to a defect in the optical card I, the value of the integrating circuit 22 does not change or changes only slowly, so that a normal detection result can be obtained for a while.

The data clock generation section 16 generates a data clock that becomes a reference when reading data bit 3 based on the position information of the reference lines 6a and 6b, and is configured to generate a data clock that is a reference when reading data bit 3 based on the position information of the reference lines 6a and 6b. Generation circuit 3
3, a timing comparison circuit 34, and an integration circuit 35.

The oscillation circuit (VCO) 31 outputs a clock having a frequency N times (N=integer) the frequency of the data clock to be finally generated.

The frequency dividing circuit 32 manually outputs the average position information of the left reference line 6a sent from the reference line detection unit 15,
The clock from the oscillation circuit 31 is synchronized with the output.
/N and outputs the data clock.

The pulse generating circuit 33 generates a pulse at a position corresponding to the distance between the left and right reference lines 6a and 6b based on the above-mentioned average position of the data clock.

The timing comparison circuit 34 compares the timing of the detection signal of the right reference line 6b and the pulse from the pulse generation circuit 33. Note that the detection of the reference line 6b on the right side does not necessarily need to be based on average position information by the reference line detection unit 15.

The integration circuit 35 integrates the output of the timing comparison circuit 34 and feeds it back to the oscillation circuit 31 to set the clock frequency.

First, generation of a data clock will be explained using FIGS. 4 and 5.

When a clock having a frequency N times that of the data clock outputted from the oscillation circuit 31 is cleared by the frequency dividing circuit 32 using the average position signal of the left reference line 6a sent from the reference line detection section 15, the frequency dividing circuit 32 is cleared as shown in FIG. Thus, a data clock synchronized with the average position signal can be obtained instantaneously. In this case, the larger the value of N, the smaller the phase error.

By the way, the left and right reference lines 6a.

The distance between the data bits 6b and 6b is usually several tens of times the distance of the data bit 3, but in this embodiment, it is 20.5 times the distance. Therefore, as shown in FIG. 5, the frequency of the data clock frequency-divided based on the average position of the reference line 6a is 20.
A pulse is generated by the pulse generating circuit 33 at the position of the 5th bit.

Then, the timing comparison circuit 34 compares the timing of this pulse with the position signal of the right reference line 6b extracted from the read signal. If the frequency of the divided data clock is correctly synchronized with the position signal, the two timings will be equal. Also, if the frequency of the data clock is too high, the timing of the 20.5th bit pulse is l? ,〈If it is the other way around, it will be delayed.

Roughly speaking, when the output from the timing comparison circuit 34 is fed back to the oscillation circuit 31 via the integration circuit 35, the frequency is set according to the comparison result.

Through the above operations, an extremely accurate data clock is generated.

Next, FIG. 6 shows another embodiment of the present invention. In this embodiment, the oscillation circuit 31 of FIG. 1 is replaced with a frequency synthesizer 40 as shown. This makes it possible to obtain a more stable data clock.

In addition, although the above embodiment shows a case where a line sensor is used as a reading sensor, it can be expanded to a reading device that uses an area sensor. In the case of a format in which the recording areas 62 are intersected, a horizontal data clock can be generated based on the vertical reference line 60, and a vertical data clock can be generated based on the horizontal reference line 61. can be generated.

[Effects of the Invention] As described above, the optical card reading device of the present invention includes a reference line detection section that outputs an average position signal of the reference line from a read signal of the reference line, and an average position signal of the reference line. By including a data grotter generation section that generates a reference data clock when reading the above data bits based on becomes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a timing chart showing an example of a timing comparison circuit. FIG. 4 is a time chart illustrating a method of phase synchronization of data clocks. A time chart explaining the operation, FIG. 6 is a block diagram showing another embodiment of the present invention, FIG. 7 is a diagram showing an example of the format of an optical card when using an area sensor, and FIG. 8 is a conventional reading device. FIG. 9 is a diagram showing the optical system of the reading device, and FIG. 10 is a diagram schematically showing the configuration of the reading device. l: Optical card 3: Data bit 4: Data tracks 6a, 6b: Reference line 20: Reference line detection circuit 21: Timing comparison circuit 22; Integrating circuit 23 31: Oscillator circuit 32 33: Pulse generation circuit 34: Timing comparison circuit 35 : Integrating circuit 40: Frequency synthesizer: Pulse generator: Frequency dividing circuit

Claims (3)

[Claims] (1) A data track consisting of multiple data bits,
In an optical card data reading device for reading an optical card having a plurality of data areas formed in parallel along a reference line extending in a direction perpendicular to the data track, an average position of the reference line is determined based on a read signal of the reference line. The reference line detection section includes a reference line detection section that outputs a signal, and a data clock generation section that generates a data clock that is a reference when reading the data bits based on the average position signal of the reference line. , a reference line detection circuit that detects the reference line and outputs a detection signal; an output circuit that outputs an average position signal of the reference line based on the detection signal from the reference line detection circuit; The data clock is generated by a timing comparison circuit that inputs the output and the output of the output circuit and compares the timing of both outputs, and an integration circuit that integrates the output of the timing comparison circuit and outputs it to the output circuit. The section includes an oscillation circuit that outputs a clock having a frequency N times (N = integer) of the data clock to be generated, and an average position signal from the reference line detection section that is inputted and synchronized with the signal to output the clock from the oscillation circuit. a frequency divider circuit that divides the clock frequency of 1/N to obtain a data clock; a pulse generation circuit that outputs a pulse at a position corresponding to the distance between the reference lines of the data clock based on the above average position; It consists of a timing comparison circuit that compares the timing of detection signals of adjacent reference lines and the pulse, and an integration circuit that integrates the output of the timing comparison circuit and feeds it back to the oscillation circuit to set the frequency. Features: Optical card data reading device. (2) The optical card data reading device according to claim 1, wherein the oscillation circuit is constituted by a frequency synthesizer. (3) The optical card data reading device according to claim 1, wherein the reading sensor is an area sensor.