JPH0284431U - - Google Patents
Info
- Publication number
- JPH0284431U JPH0284431U JP16419988U JP16419988U JPH0284431U JP H0284431 U JPH0284431 U JP H0284431U JP 16419988 U JP16419988 U JP 16419988U JP 16419988 U JP16419988 U JP 16419988U JP H0284431 U JPH0284431 U JP H0284431U
- Authority
- JP
- Japan
- Prior art keywords
- digital signal
- digital
- fader
- switching
- operation section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005562 fading Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図ａ，ｂは本考案の説明に供するタイミング
チヤート図。
１……制御装置、２……デイジタル信号選択回
路、３……ＤＡＩＦ復調器、４……デイジタルフ
イルタ、５……Ｄ／Ａ変換器、６，７……インバ
ータ、８……ＡＮＤ回路、１０〜１２……入力端
子、１３……出力端子、ＳＷ１〜ＳＷ３……スイ
ツチ、Ｑ１〜Ｑ３……トランジスタ、Ｄ１〜Ｄ３
……発光ダイオード。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIGS. 2a and 2b are timing charts for explaining the present invention. DESCRIPTION OF SYMBOLS 1... Control device, 2... Digital signal selection circuit, 3... DAIF demodulator, 4... Digital filter, 5... D/A converter, 6, 7... Inverter, 8... AND circuit, 10 ~12...Input terminal, 13...Output terminal, SW1-SW3...Switch, Q1-Q3...Transistor, D1-D3
...Light emitting diode.
Claims (1)
デイジタル信号を選択すべく操作される入力切換
操作部と、 該入力切換操作部の操作に基づき、対応するデ
イジタル信号を選択する選択回路と、 該選択回路によつて選択されたデイジタル信号
をフエードイン／フエードアウト可能なデイジタ
ルフエーダー回路と、 デイジタル信号に含まれるクロツク信号にロツ
ク可能なＰＬＬ回路と、 選択された一のデイジタル信号から他のデイジ
タル信号への切換時、前記入力切換操作部の操作
に基づき前記デイジタルフエーダーをフエードア
ウトし、前記一のデイジタル信号をデイジタルゼ
ロ状態とした後、前記選択回路を前記一のデイジ
タル信号から他のデイジタル信号に切換え、その
後前記ＰＬＬ回路が前記他のデイジタル信号にロ
ツクしたことを検出した後、前記デイジタルフエ
ーダーをフエードインする制御手段とからなるこ
とを特徴とするデイジタル信号切換装置。[Claims for Utility Model Registration] An input switching operation section that is operated to select one digital signal from among a plurality of input digital signals, and a corresponding digital signal is selected based on the operation of the input switching operation section. a digital fader circuit capable of fading in/out a digital signal selected by the selecting circuit; a PLL circuit capable of locking to a clock signal included in the digital signal; and a selected one digital signal. When switching from one digital signal to another, the digital fader is faded out based on the operation of the input switching operation section to bring the first digital signal to a digital zero state, and then the selection circuit is switched from the first digital signal to the digital fader. A digital signal switching device comprising control means for switching to another digital signal and then fading in the digital fader after detecting that the PLL circuit has locked to the other digital signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16419988U JPH0438592Y2 (en) | 1988-12-19 | 1988-12-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16419988U JPH0438592Y2 (en) | 1988-12-19 | 1988-12-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0284431U true JPH0284431U (en) | 1990-06-29 |
| JPH0438592Y2 JPH0438592Y2 (en) | 1992-09-09 |
Family
ID=31449602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16419988U Expired JPH0438592Y2 (en) | 1988-12-19 | 1988-12-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438592Y2 (en) |
-
1988
- 1988-12-19 JP JP16419988U patent/JPH0438592Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0438592Y2 (en) | 1992-09-09 |
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