JPH028457Y2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Industrial Application Field The present invention relates to a sampling area initialization circuit used in a sampling area setting circuit employed in a video camera.

(b) Prior Art Auto-focus control mechanisms that sample the luminance signal obtained from a video camera and rotate the focus ring so that the high-frequency portion of the signal is maximized have been used in various video cameras. has been adopted. However, most of them perform autofocus control by using a certain range in the center of the screen as a sampling area (focus control area), and whether you like it or not, the focus is always on the center of the screen, making it difficult to use. This caused an inconvenience.

Therefore, the applicant proposed a method of arbitrarily changing the focus control area and displaying the area on an electronic view indexer in Japanese Patent Laid-Open Nos. 59-107685 and 1987-105773. These methods perform autofocus control by setting a sampling area at an arbitrary position on the screen, and display the sampling area in an electronic viewfinder.

(c) Problems to be solved by the invention However, in the case of the conventional example described above, the sampling area is not fixed at a specific position when the power is turned on;
Also, it may take time to restore the sampling area to the center of the screen during shooting.

(d) Means for Solving the Problems Therefore, the present invention is characterized in that a conventional video camera is provided with an initialization circuit that initializes the stored value of the register for setting the sampling area when the power is turned on or a reset operation is performed. do.

(E) Effect Therefore, in the present invention, the sampling area is set to the initial position when the power is turned on, and the sampling area is also set to the initial position when the reset operation is performed.

(F) Embodiment The present invention will be described below with reference to an illustrative embodiment.

First, FIG. 2 is a circuit block diagram showing the overall configuration of this embodiment.

First, a luminance signal Y in a video signal obtained from an image sensor is amplified by a preamplifier 1, and a sampling circuit 2 samples only the luminance signal corresponding to a sampling area. This sampling output is input to a high pass filter 3, and only high frequency components are separated. This high-frequency component is amplitude-detected by the detection circuit 4, and the detection output is output by the integration circuit 5.
is integrated for each field. This integrated output is delayed by one field in the delay circuit 6. The comparison circuit 7 compares the levels of the integral output and the delayed integral output, and inputs the comparison output to the focus motor control circuit 8. Therefore, the focus control motor is driven in a direction in which the integral output increases, and the focus ring (not shown) is rotated to the convergence point position.

The configuration described above is a well-known configuration in focus control mechanisms.

The generation of sampling pulses and the display of sampling areas will be explained below.

First, in this example, the sampling area is determined by selecting either a small basic sampling area, which is made up of 64 blocks made by dividing the screen vertically and horizontally into eight equal parts, and an expanded sampling area, which is made up of four blocks each. ing. FIG. 3 schematically shows the sampling area display state when the expanded sampling area is selected at the center of the screen.

The selection output of the area selection means 9, which has 64 selection buttons arranged in a matrix on the side of the cabinet of the video camera, is sent to the sampling area selection circuit 10.
The decoded data is decoded at , and the decoded outputs of 3 bits each are input to the vertical register 11 and the horizontal register 12 . Each of the registers 11 and 12 is a 3-bit register, and determines the upper right block position of the sampling area.

On the other hand, from the synchronization pulse generation circuit 13, a vertical blanking pulse V including a vertical synchronization signal, a horizontal blanking pulse H including a horizontal synchronization signal, and a color subcarrier C are derived, and the horizontal blanking pulse H is input. The output of the 1/32 frequency divider circuit 14 is used as the counting input of the vertical counter 15. The 1/32 frequency divider circuit 14 and the vertical counter 15 have the vertical blanking pulse V as a reset input,
A 3-bit vertical counter 15 counts blocks on the screen vertically for each field in synchronization with the video signal. Similarly, in view of the fact that the phase of the color subcarrier C is inverted for each frame, the phase inversion circuit 16 to which the color subcarrier C is input is supplied with a vertical blanking pulse in order to invert the phase of the color subcarrier C at the frame period. The output of the 1/4 frequency divider circuit 17 which inputs V is used as an inversion control input. This phase inversion output is 1/24 frequency divider circuit 18
The frequency-divided output is input to a 3-bit horizontal counter 19. Therefore, the horizontal counter 19 counts blocks in the horizontal direction for each horizontal scan in synchronization with the video signal. Incidentally, the phase inversion circuit 16
The 1/4 frequency divider circuit 17 is provided in consideration of the display form of the sampling area of this embodiment, and is not particularly necessary for focus control.

A vertical comparison circuit 16, which receives the output of the vertical counter 15 and the output of the vertical register 11, detects the corresponding block row and the next block row and generates a vertical comparison output. Further, a horizontal comparison circuit 21 which receives the output of the horizontal counter 19 and the output of the horizontal register 12 detects the corresponding block column and the next block column and outputs a horizontal comparison output. The basic sampling pulse generation circuit 22, which receives the horizontal and vertical comparison outputs, derives the AND output of both outputs as a basic sampling pulse.
This basic sampling pulse generates a pulse corresponding to a basic sampling area of 2 blocks x 2 blocks on the screen.

On the other hand, vertical expansion circuit 2 inputs the vertical comparison output.
No. 3 outputs a vertical expansion output for four blocks in the vertical direction, which is twice the pulse width of the vertical comparison output. Similarly, the horizontal expansion circuit 24 to which the horizontal comparison output is input generates horizontal expansion output for four blocks in the horizontal direction, which is obtained by expanding the pulse width of the horizontal comparison output by twice. The expansion pulse generation circuit 25 which receives these vertical expansion output and horizontal expansion output derives the AND output of both outputs as an expansion sampling pulse. This extended sampling pulse generates a pulse corresponding to an extended sampling area of 4 blocks x 4 blocks on the screen.

FIG. 4 shows the vertical comparator circuit 20 and the vertical expansion circuit 23.
FIG. 2 is a circuit block diagram showing a specific configuration of the circuit. As is clear from this figure, the vertical comparison circuit 23 includes first and second coincidence detection circuits 20a and 29b, and the first coincidence detection circuit 20a detects when the vertical counter output and the vertical register output match. The second coincidence output detection circuit 2 generates a coincidence output.
0b generates an output when the vertical counter output and the output of the first adder circuit 20c match. Note that the first adder circuit outputs an output obtained by adding 1'' to the vertical register output, and the second coincidence detection output corresponds to the block next to the block corresponding to the vertical register output. The coincidence output and the second coincidence output will be emitted successively, and the first OR circuit 20d which inputs both coincidence outputs is connected to the vertical register 11.
A vertical comparison output of the pulse width corresponding to the block position stored by the block position and the next block position is derived.

Next, in the vertical expansion circuit 23, second and third adder circuits 23b and 23c input the vertical register output.
The second and third addition outputs are derived by adding "2" and "3" to the vertical register output, and the third coincidence detection circuit 23a derives the second and third addition outputs by adding "2" and "3" to the vertical register output.
The fourth coincidence detection circuit 23d compares the vertical counter output and the third addition output.
Therefore, the third match output will occur following the second match output, and the fourth match output will occur following the third match output. Therefore, the vertical comparison output and the third and fourth
The second OR circuit 23e which receives the matching application outputs a vertically extended output having a pulse width corresponding to four block rows including the block row corresponding to the vertical register output. The upper limit of the addition output of each of the first, second, and third addition circuits 20c, 23b, and 23c described above is set to 7.

With the above-described configuration, a vertical comparison output and twice the vertical expansion output are derived, but the horizontal comparison circuit 2
1 and the horizontal expansion circuit 24 are also the vertical comparison circuit 2 described above.
0 and the vertical expansion circuit 23, illustration and description thereof will be omitted.

On the other hand, the sampling pulse selection circuit 26 which inputs the basic sampling pulse and the extended sampling pulse selects one of the outputs according to the output of the flip-flop 27 and uses the selected pulse as the sampling pulse of the sampling circuit 2, and the sampling pulse selection circuit 26 inputs the basic sampling pulse and the extended sampling pulse. Alternatively, a luminance signal corresponding to the extended sampling area is separated for focus control. The flip-flop 27 uses the output of the expansion selection means 33 including the area width setting button as a trigger input, and the flip-flop 27 repeats inversion every time the area width setting button is pressed.

Further, the selection pulse is used as a signal input to the selection circuit 31. This selection circuit 31 uses as a control input the 1/2 frequency division output of the 1/2 frequency divider circuit 28 which has the vertical blanking pulse V as a reset input and the horizontal blanking pulse H as a counting input. Only the selection pulse is input to the display signal multiplexing circuit 32 as a selection output. This display signal multiplexing circuit 32 has a luminance signal as a signal input, a selection output as a signal input, and sets odd lines in the basic sampling area or extended sampling area to the black level.

FIG. 5 shows a specific circuit configuration of the display signal multiplexing circuit 32. That is, the display signal multiplexing circuit 3
2, a multiplexed signal is supplied from the emitter of the first transistor Q1 whose base input is the preamplifier output (luminance signal) to a signal processing circuit including an electronic viewfinder, and a collector/emitter is connected between the base of the first transistor Q1 and the ground. Connect the second
By using the selection output as the base input of the transistor Q2, the base of the first transistor Q1 is grounded by the selection output. Therefore, when the selection output is generated, the multiplexed signal becomes 0 level, that is, black level. Therefore, thin black horizontal stripes are displayed in the basic sampling area or extended sampling area on the electronic view indexer. If white horizontal stripes are used instead of black horizontal stripes, the selection output may be input directly to the ground of the first transistor Q1 to bring the first transistor to the saturation level. Furthermore, 1/2
The frequency dividing ratio of the frequency dividing circuit 28 does not necessarily have to be 1/2, and may be a 1/n frequency dividing circuit that becomes high level once every n lines.

With the above-described configuration, it is possible to set the position and width for focus control.

However, this basic sampling area or extended sampling area must be returned to the center of the screen when the power is turned on or by a reset scan. Therefore, in this embodiment, a preset circuit is provided for initialization. Figure 1 shows the reset operation means 2.
9, an initialization circuit 30, and a vertical/horizontal register 11,
12 connection relationships are specifically shown. As is clear from this figure, the vertical registers 11 are arranged in the first, second, and third registers.
It consists of flip-flops 11a, 11b, and 11c, and the horizontal register 12 also consists of fourth, fifth, and sixth flip-flops 12a, 12b, and 12c.
Each flip-flop receives a 6-bit sampling area selection output as data input, and uses a latch pulse derived from the area selection means 9 to latch the selected position when an area is selected. On the other hand, a reset switch constituting the reset operation means 29
SW constitutes a discharge path for the capacitor C in the initialization circuit 30. This capacitor C has a resistor R connected in series between the power source and ground to form an integrating circuit, and the connection point thereof is used as an input to a comparator 30a. Therefore, when the power is turned on, no comparator output is generated until the integral output reaches a certain level.
The preset output will be generated after a certain period of time after power is turned on. Also, reset switch SW
When the capacitor C is closed, the capacitor C is temporarily discharged, and a preset pulse is generated even after a certain period of time after the reset operation. This preset pulse is applied to the first and fourth flip-flops 11.
The second, third, and
Fifth and sixth flip-flops 11b, 11c, 1
The signals are input to set terminals 2b and 12c, respectively. Therefore, the vertical register output and horizontal register output will be preset to "3". At the same time, the preset pulse will also reset the flip-flop 27, and the sampling pulse selection circuit 26 will select the sampling pulse. Therefore, by generating the preset pulse,
When the sampling area is expressed in two-dimensional coordinates,
The basic sampling area is defined as four blocks: 3, 3, 3, 4, 4, 3, 4, 4. In the embodiment described above, the basic sampling area was selected at initialization, but if the extended sampling area is to be selected, it is sufficient to preset each register 11 and 12 to "2" and set the flip-flop 27. Not until now.

(g) Effects of the invention Therefore, in this invention, the sampling area is always initialized to the center of the screen when the power is turned on, and it is also easily initialized by the reset switch, so the effect of improved operability is large. It is.

[Brief explanation of the drawing]

Each of the figures shows an embodiment of the present invention. Figure 1 is a circuit diagram of the main parts of a preset circuit and horizontal and vertical registers, Figure 2 is an overall circuit book diagram, and Figure 3 is a schematic diagram of a pattern in an electronic viewfinder. The explanatory diagram, FIG. 4, is a main part circuit diagram of a vertical comparator circuit and a vertical expansion circuit, and FIG. 5 is a specific circuit diagram of a display signal multiplexing circuit. 29... Reset operation means, 30... Preset circuit.

Claims (1)

[Claims for Utility Model Registration] A vertical counter that receives a vertical synchronization signal as a reset input and counts the frequency-divided output of the horizontal synchronization signal, a vertical register that stores the vertical position of a sampling area, and each of the vertical counter and the vertical register. a vertical comparison circuit that detects coincidence of outputs, a horizontal counter that uses a horizontal synchronization signal as a reset input and counts the multiplied output of the horizontal synchronization signal, a horizontal register that stores the horizontal position of a sampling area, and the horizontal counter and the horizontal register. a horizontal comparison circuit that detects coincidence of each output of the two comparison circuits; a sampling pulse generation circuit that uses an AND output of the outputs of the two comparison circuits as a sampling pulse; and a sampling circuit that samples high-frequency components in the video signal using the sampling pulse. , a sampling area setting circuit for a video camera comprising a focus control circuit that rotates a focus ring so that the sampling output is maximized, and a sampling area selection circuit that sets arbitrary values in both registers. 1. A sampling area initialization circuit, comprising: an initialization circuit that presets both registers to initial values corresponding to a sampling area at the center of the screen by a power-on operation or a reset operation.