JPH0284726A - Aluminum wiring - Google Patents
Aluminum wiringInfo
- Publication number
- JPH0284726A JPH0284726A JP23772488A JP23772488A JPH0284726A JP H0284726 A JPH0284726 A JP H0284726A JP 23772488 A JP23772488 A JP 23772488A JP 23772488 A JP23772488 A JP 23772488A JP H0284726 A JPH0284726 A JP H0284726A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- glass
- cvd
- added
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052782 aluminium Inorganic materials 0.000 title claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title claims description 4
- 239000011521 glass Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract description 2
- 150000002894 organic compounds Chemical class 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- MCULRUJILOGHCJ-UHFFFAOYSA-N triisobutylaluminium Chemical compound CC(C)C[Al](CC(C)C)CC(C)C MCULRUJILOGHCJ-UHFFFAOYSA-N 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 10
- 229910052681 coesite Inorganic materials 0.000 abstract 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract 5
- 239000000377 silicon dioxide Substances 0.000 abstract 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract 5
- 229910052682 stishovite Inorganic materials 0.000 abstract 5
- 229910052905 tridymite Inorganic materials 0.000 abstract 5
- 239000000463 material Substances 0.000 abstract 1
- 239000005360 phosphosilicate glass Substances 0.000 abstract 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置のAffi系配線系間線る。[Detailed description of the invention] [Industrial application field] The present invention relates to lines between Affi-based wiring systems of semiconductor devices.
従来、半導体集積回路のAl系配線には保護膜として5
in2系ガラス及びその表面に窒化珪素膜が形成されて
いる。 Sin、系ガラスは通常CVDを用いて堆積さ
れ、窒化珪素は通常プラズマCvDを用いて堆積されて
いる。Conventionally, 5 was used as a protective film for Al-based wiring in semiconductor integrated circuits.
A silicon nitride film is formed on the in2 glass and its surface. Sin-based glasses are typically deposited using CVD, and silicon nitride is typically deposited using plasma CVD.
上記のようなAl系配線は、半導体集積回路をセラミッ
クパッケージに封じ込める際のように400℃以上の温
度に晒されると、配線中にボイドを発生し、断線を引き
起こすという問題がある。この問題はこれまでそのメカ
ニズムが解明されていないため、有効な解決策が提案さ
れていない。たとえば、窒化珪素膜の内部応力を通常の
圧縮から引っ張りになるように、プラズマCvDでの形
成条件を変化させるとボイドが発生しにくいが、この窒
化珪素膜はひび割れが入りやすく実用にならない。When the above-mentioned Al-based wiring is exposed to temperatures of 400° C. or higher, such as when a semiconductor integrated circuit is sealed in a ceramic package, there is a problem in that voids are generated in the wiring, causing disconnection. Since the mechanism of this problem has not been elucidated so far, no effective solution has been proposed. For example, if the formation conditions in plasma CVD are changed so that the internal stress of the silicon nitride film is changed from normal compression to tension, voids are less likely to occur, but this silicon nitride film is prone to cracking and is not practical.
本発明は上記問題点を解決したアルミニウム系配線を提
供することにある。An object of the present invention is to provide an aluminum-based wiring that solves the above-mentioned problems.
上記目的を達成するため、本発明のアルミニウム系配線
においては、半導体集積回路のAl系配線にAl1を添
加した5in2系ガラスの保護膜を有するものである。In order to achieve the above object, the aluminum-based wiring of the present invention has a protective film of 5in2-based glass doped with Al1 on the Al-based wiring of a semiconductor integrated circuit.
CvDで堆積した保護膜のSin、系ガラスの表面にプ
ラズマCvDで窒化珪素膜を堆積する場合、ひび割れを
防止するために圧縮の内部応力を持つ窒化珪素膜が堆積
される。そのため、Sin、系ガラスは窒化珪素膜から
引っ張り応力(10”din/aJ台)を受けることに
なる。引っ張り応力を受けたSiO,系ガラスは金属原
子を吸収しようとする性質が増進され、Al2JJK子
を吸収することによってAΩ配線にボイドを作る原因と
なる。そこでSin、系ガラスに^悲を予め添加すれば
、配線のAl原子はSiO□系ガラスに吸収されること
がなく、Al系配線に発生するボイドを防止することが
できる。When a silicon nitride film is deposited by plasma CvD on the surface of a Si-based protective film deposited by CvD, a silicon nitride film having compressive internal stress is deposited to prevent cracking. Therefore, the Si-based glass receives tensile stress (on the order of 10" din/aJ) from the silicon nitride film. The SiO-based glass that receives the tensile stress has an enhanced ability to absorb metal atoms, and the Al2JJK This causes voids to be created in the AΩ wiring. Therefore, if Si is added to the Si-based glass in advance, the Al atoms in the wiring will not be absorbed by the SiO□-based glass, and the Al-based wiring will be formed. It is possible to prevent voids from occurring.
以下に本発明の実施例を図を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図はその一例である0図において、眉間絶縁膜1を
有する基板2上に、Al−1%Si膜を形成した後、フ
ォトレジスト工程とドライエツチング工程とによって配
線パターン3を形成し、CVDによってAΩが添加され
た燐ガラス4を1−堆積する。FIG. 1 is an example of this, in which an Al-1% Si film is formed on a substrate 2 having an insulating film 1 between the eyebrows, and then a wiring pattern 3 is formed by a photoresist process and a dry etching process. A phosphorus glass 4 doped with AΩ is deposited by CVD.
次いでプラズマCVDによって窒化珪素膜5を0.3゜
堆積することによって第1図の構造を得る。Next, a silicon nitride film 5 of 0.3° is deposited by plasma CVD to obtain the structure shown in FIG.
Alが添加されたSiO□系ガラスをCVDによって形
成するには、Sin、系ガラスの原料ガスにAfl有機
化合物(トリイソブチルアルミニウムやトリメチルアル
ミニウム等)を混入させればよい、また、5101系ガ
ラスをCvOによって形成した後にAlをイオン注入し
てもよい。In order to form Al-doped SiO□-based glass by CVD, it is sufficient to mix Afl organic compounds (triisobutylaluminum, trimethylaluminum, etc.) into the raw material gas of the Si-based glass. Al may be ion-implanted after forming with CvO.
上記のAl系配線は、450@C程度の熱処理ではボイ
ドの発生が見られなかった。No voids were observed in the above-mentioned Al-based wiring after heat treatment at about 450@C.
以上のように本発明によれば400〜500℃の温度に
晒されてもボイド発生のない半導体集積回路のi系配線
を得ることができる効果を有するものである。As described above, according to the present invention, it is possible to obtain i-system wiring for semiconductor integrated circuits that does not generate voids even when exposed to temperatures of 400 to 500°C.
第1図は本発明を説明する模式図である。
1・・・層間絶縁[2・・・基板
3・・・配線パターン 4・・・Alを添加した燐ガ
ラス5・・・窒化珪素膜FIG. 1 is a schematic diagram illustrating the present invention. 1... Interlayer insulation [2... Substrate 3... Wiring pattern 4... Phosphorus glass added with Al 5... Silicon nitride film
Claims (1)
iO_2系ガラスの保護膜を有することを特徴とするア
ルミニウム系配線。(1) S with Al added to Al-based wiring in semiconductor integrated circuits
An aluminum-based wiring characterized by having a protective film of iO_2-based glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23772488A JPH07112009B2 (en) | 1988-09-21 | 1988-09-21 | Aluminum wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23772488A JPH07112009B2 (en) | 1988-09-21 | 1988-09-21 | Aluminum wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0284726A true JPH0284726A (en) | 1990-03-26 |
| JPH07112009B2 JPH07112009B2 (en) | 1995-11-29 |
Family
ID=17019553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23772488A Expired - Lifetime JPH07112009B2 (en) | 1988-09-21 | 1988-09-21 | Aluminum wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07112009B2 (en) |
-
1988
- 1988-09-21 JP JP23772488A patent/JPH07112009B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07112009B2 (en) | 1995-11-29 |
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