JPH0284821A - Key input circuit - Google Patents

Abstract

PURPOSE:To attain discrimination at twice the key switching state by changing an output terminal state to three states of high, low level, and high impedance, and changing an input terminal state to a state of pull-up/down or high impedance. CONSTITUTION:The states of terminals (30-32) are read in by setting the output terminals (2-4) of an output mechanism 1 at H levels, and the input terminals (30-32) of an input mechanism 29 at the pulldown states. A key is detected assuming the key on a matrix 33 for active-high is depressed when at least either the terminals (30-32) is set at the H level, and an operation is shifted to the detection of a key matrix 34 for active-low when it is not set at the H level. Also, the state of the terminals (30-32) are read in by setting the terminals (2-4) at L levels. The key is detected assuming that the key on the matrix 34 ls depressed when at least either of the terminals (30-32) is set at the L level, and the operation is shifted to the detection of a matrix 33 when it is not. In such a way, it is possible to use a circuit by combining both matrices 33 and 34, and to discriminate at twice the key switching state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to electronic equipment, and particularly to an input method and an input/output mechanism for equipment using a microcomputer.

[Conventional technology]

Conventionally, this type of key manual system has an output terminal called a KEY source and an input terminal called a KEY input, as shown in Figs. 6 and 7, and the state of the switch on the matrix activates one KEY source. KEY at that time
Reading was performed by sequentially repeating the process of reading an input, activating another KEY source, and reading the current KEY input. Depending on the conditions of use, either an active high or an active low KEY matrix has been used depending on the hardware or software of the microcomputer.

In this method, the KEY source has two states, high level and low level, and the KEY input has 7 active high KE states.
A Y matrix required a pulled-down input mechanism, and an active low required a pulled-up input mechanism.

[Problem to be solved by the invention]

In the above-mentioned conventional KEY input method, when there are m KEY sources and n KEY inputs, the K'EY matrix has mXn intersections, so it was only possible to read the states of mXn switches.

[Means to solve the problem]

The KEY input circuit of the present invention has an output mechanism that takes three output states: high level, low level, and high impedance, a backflow prevention diode, a KEY switch, and a pull-up and pull-down state that can be switched. It has an input mechanism.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the invention. 1 means its output is high.
The output mechanism has three states: level, low level, and high impedance, and each output terminal is numbered 2 to 4.

5 to 10 are reverse current prevention diodes, 11 to 28 are KEY switches, and 29 is a pull-down or pull-down input.
The input mechanism can be switched up and has 30 to 32 terminals, respectively. Also, 33 is a KEY matrix for active high, and 34 is a key for active low.
It is a matrix.

The KEY switch is imported as follows.

1. Detection of active high matrix The output terminals 2 to 4 of the output mechanism 1 are set to high level, the input terminals 30 to 32 of the input mechanism 29 are pulled down, and the states of the input terminals 30 to 32 are read.

If at least one of the input terminals 30 to 32 is at a high level, the KEY switch on the active high matrix 33 is detected as being pressed, and if not, the active low key matrix is detected. Transfer to.

2. Scanning of KEY matrix 33 for active high When it is determined that a switch in the active high key matrix 33 is pressed, scan which switch is pressed.

The output terminal 2 of the output mechanism 1 is set to a high level, and the output terminals 3 and 4 are set to a high impedance state. Input mechanism 2
90 input terminals 30 to 32 are pulled down and their terminal states are input.

This allows the states of switches 11, 14, and 17 to be read.

Next, while keeping the input terminal pulled down, set output terminal 3 of output mechanism 1 to high level, and set 2°4 to high impedance.0 Next, read the input terminal state and get 12.1
The status of switches 5 and 18 can be read.

Similarly, while the input remains pulled down, output terminal 4 is set to high level, and terminals 2 and 3 are set to high impedance.

Then, by reading the input terminal state, the state of the switch on 13.18.19 can be read.

3. Set the output terminals 2 to 4 of the input/output mechanism 1 of the active low KEY matrix to low level, pull up the input terminals 30 to 32 of the input mechanism 29, and read the states of the input terminals 30 to 32. .

If at least one of the input terminals 30 to 32 is at low level, K on the acute low key matrix 34
If the EY switch is pressed, the KEY switch is detected, and if not, the process proceeds to detecting the KEY matrix for active high.

4. Scanning the active row KEY matrix If it is determined that a switch in the active row key matrix 34 is pressed, scan which switch is pressed.

The output terminal 2 of the output mechanism 1 is set to a low level, and the output terminals 3 and 4 are set to a high impedance state. Input mechanism 2
The input terminals 30 to 32 of 9 are pulled up and the terminal states are input.

This allows the states of switches 20, 23, and 26 to be read.

Next, while the input terminal remains pulled up, the output terminal 3 of the output mechanism 1 is set to a low level, and 2.4 is set to high impedance. Next, when reading the input terminal status, 21
, 24.29 can be read.

Similarly, while the input remains pulled up, output terminal 4 is set to low level, and terminals 2 and 3 are set to high impedance.

Next, by reading the input terminal state, the state of the switch at 22.25°28 can be read.

A flow chart of the above operation is shown in FIG.

[Example 2] FIG. 3 shows Example 2 of the present invention. 35 is active
Output latch for high, 36 output latch for active/low, 37 KEY data selector, 38 output logic circuit, 39 backflow prevention diode, 40 KEY switch, 41 input logic circuit, 42 input latch, 4
3 is an active memory latch.

When "1" is put into the active memory latch 43 and "1111" is put into the active memory latch 43, the output terminals 44 to 47 become high level and the input terminals 49 to 51
is pulled down. The state of the input terminal at this time is read into the latch 42.

If it is determined that there is a KEY input based on the read data, data of "1000" is set in the "output switch" for active high.As a result, the output terminal 44 becomes high level, and 45, 46, and 47 become high level. It becomes high impedance.The state of the input terminal at this time is latched into the input latch 42 and read.

“0100”, “0010”, “0001” in the output latch
By sequentially outputting the data and doing the same, scanning of the KEY for active high can be performed.

Next, when "0" is put into the active memory latch and data "1111" is set into the active low output latch, the output terminals 44 to 47 are set by the output logic circuit.
A low level is output.

At this time, the input is pulled up and the input latch has KE.
When the Y switch is pressed, 1 is latched into the input latch by the input logic circuit.

In other words, whether the KEY matrix is for active high or active low, if the momentary switch is pressed, "1" can be read.

When active low, set and input data in the same way as when active high.
The row KEY matrix can be scanned.

Embodiment 2 is an example in which the control of the input/output circuit is partially implemented in hardware to reduce the burden on the program.

[Embodiment 3] In Embodiment 3, the present invention is applied to a system in which a segment signal of an LCD display is used as a KEY source signal.

In Fig. 4, 52 is a display segment latch, 53 is an active high output, 64 is an active low output latch, 55 is a KEY data selector, 56 is an output data selector, and 57 is an output logic. circuit, 58 is a display common latch, 59 is an LCD display, 6
0 is KEY for active high and active low
61 is an input logic circuit, 62 is an input latch, 63 is an active memory latch, and 64 is an output data selection latch.

In addition, FIG. 5 shows a timing chart of Embodiment 3. In the figure, COMI and C0M2 are display common latches 5.
With the output signal from 8, 81. S2... are output signals from the output logic circuit 57.

1 is a state diagram when the input of the input logic circuit 61 is opened. Therefore, when the KEY switch is pressed, the level of 1 changes.

In FIG. 5, a period 65 is a display period, during which data in the display segment latch 52 passes through an output data selector 56 and is output through an output logic circuit 57. This signal and the output of the display common latch 58 cause the LCD display to turn 0N10FF. Further, during the display period of 65, the input becomes high impedance, so even if the KEY switch is pressed, the display is not affected.

The period 66 is the KEY ON detection period of the active high KEY matrix, and the data of the active high output latch 53 passes through the KEY data selector 55, the output data selector 56, and the output logic circuit 57. is output from. At this time, the output from the display common latch 58 is at an intermediate potential, and the display is OFF.
becomes.

Further, since the input terminal is pulled down by the action of the 610 input logic circuit, the input terminal becomes low level if the KEY switch is not pressed, and becomes high level if it is pressed.

The 670 period is the KEY ON detection period of the active low KEY matrix, and the data of the active low output latches 54 passes through the KEY data selector 55, the output data selector 56, and the output logic 57. output from the circuit. At this time, the output from the display common latch 58 is at an intermediate potential, and the display is OF.
It becomes F.

Furthermore, since the input terminal is pulled up by the action of the 610 input logic circuit, it is at a high level if the KEY switch is not pressed, and is at a low level if it is not pressed.

Also, the 680 period is the KEY scanning period of the active high KEY matrix, which performs the same operation as the 66 period except that only one of the segment outputs is at high level and the others are at high impedance. .

Also, 69 is K of the active low KEY matrix.
The same operation is performed except that only one of the comparison segment outputs is at a low level and the others are at high impedance during a period of 67 in the EY scanning period.

Embodiment 3 is applied to an example in which the display output of an LCD is used as a KEY source, and the terminal efficiency of the IC can be further increased than before.

〔Effect of the invention〕

As explained above, the present invention provides a high
The KEY matrix for active high can be changed to three states: level, low level, and high impedance, and by changing the state of the input terminal to pull up, pull down, or in addition to the high impedance state. It is now possible to use the KEY matrix for active rows in combination with the same number of terminals as before (
m+n) and twice the conventional key switch (2XmXn)
This has the effect of being able to determine the state of

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, l...
・Three-value output mechanism, 2 to 4...Output terminal, 5 to l
O...Reverse current prevention diode, 11-28...
...KEY switch, 29...Input mechanism, 3
0 to 32...Input terminal, 33...KEY matrix for active high, 34...
KEY matrix for active row. FIG. 2 is a diagram showing a flowchart of the present invention. FIG. 3 is a diagram showing another embodiment of the present invention, 35...
・Output latch for active high, 36...Output latch for active low, 37...KEY
Data selector, 38...Output logic circuit, 39...Reverse current prevention diode, 40...
...KEY switch, 41...Input logic circuit, 42...Input latch, 43...Active memory latch, 44-4゛7...・・・
Output terminal, 48-51... Input terminal. FIG. 4 is a diagram showing another embodiment of the present invention, 52...
- Display segment latch, 53... Output latch for active high, 54... Output latch for group active low, 55... KEY data selector, 56...・Output data selector, 57・
... Output logic circuit, 58 ... Common latch for display, 59 ... LCD display, 60 ... KEY matrix for active high and active low, 61... Input logic circuit, 62... Input latch, 63...
...Active memory latch, 64...
Output data selection latch. FIG. 5 is a diagram showing a timing chart of the third embodiment, 65...Display period, 66...KEY ON detection period of active high KEY matrix, 67... KEY ON detection period of KEY matrix for active low, 68...Scanning period of KEY matrix for active high, 69
....Scanning period of active low KEY matrix. Figure 6 shows a conventional KEY input circuit with K for active high.
A diagram showing an example of an EY matrix, 70... Output amplifier, 71... Backflow prevention diode, 72...
...KEY switch, 73...Group pull-down resistor, 74...Input amplifier. Figure 7 shows the conventional KEY input circuit for active low K.
FIG. 3 is a diagram showing an example of an EY matrix. 75...Output amplifier, 76...Reverse current prevention diode, 77...KEY switch, 78
...Pull-up resistor, 79...Input amplifier. Agent Patent Attorney Hara Uchi

Claims (1)

[Claims] In a key matrix input circuit that scans the output terminal signal and reads it from the input terminal to read the state of the switch on the matrix, the output state of the output terminal is set to three states: high level, low level, and high impedance. It has a mechanism that allows the input terminal to pull up,
By having a pull-down mechanism and a backflow prevention diode, it is possible to switch between two key matrices: one that operates at active high and the other that operates at active low.
A microcomputer key-in circuit that can increase the number of switches on a matrix.