JPH0284882A - Picture encoding device and picture decoding device - Google Patents

Abstract

PURPOSE:To decrease the input number of addresses by selectively supplying plural variables to the address of a ROM in a ROM sequencer. CONSTITUTION:Processing is executed by a burrel shifter, etc., to convert an indefinite length code, which is packed to a constant bit number, to a form, with which the code can be inputted to an indefinite length code table, a multiplexer 44 is provided before the address input of a ROM45, which controls a burrel shifter 38, and either (l) or (n) is selected out of control variables and inputted. Thus, the number of the address inputs is decreased and the capacity of the ROM can be widely reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device for source encoding and a device for decoding image information, and particularly to encoding and decoding of indefinite length codes.

[Conventional technology]

An image encoding device using an indefinite length code word, for example, M
In the H (Modified Huffman) encoding device and the MR (Modified READ) encoding device,
For example, undefined length code words of 2 to 13 pits are packed into data of a certain length, for example, 8 bits.
In other words, it is necessary to reorganize. This is because post-encoding processing, such as storage in a storage device or output to a communication line, is easier if the bit length is constant.

For this reason, as shown in Japanese Patent Laid-Open No. 60-74776, it is known to use a shift register to convert an indefinite length code word into data of a constant length.

As shown in the block diagram of FIG. 9, the device described in the publication includes a code generation circuit 20 that converts an image into an indefinite length code word;
A first shift register 2 inputs the indefinite length code words from the code generation circuit 20 in parallel and then outputs them in series.
1, and a second shift register 22 which serially inputs the serially output indefinite length code words and then outputs them in parallel to the code memory 23.

[Problems to be Solved by the Invention] However, in the device configured as described above, the transfer from the first shift register 21 to the second shift register 22 is performed in units of one bit. That is, since an indefinite length code word is processed one bit at a time, the processing takes time and is not suitable for high-speed processing.

A solution to this problem is to use a barrel shifter and a ROM (read-only memory) sequencer to move multiple bits into one.
A method of processing in cycles was proposed by the present applicant in Japanese Patent Application Laid-Open No. 1986-63.
It is proposed as No. 54067.

This is done by providing a barrel shifter that shifts the indefinite length codeword at once by the difference between the length of the already processed part of the indefinite length codeword and the length of the part already packed to a fixed length. It is controlled by a sequencer based on ROM.

In the method described in Japanese Patent Application Laid-Open No. 63-54067, as shown in FIG. 8(a), the number l of bits of an indefinite length code word, the number m of already packed bits, and Since the three variables of the number n of bits in which code words have already been stored were manually controlled, there was a drawback that the number of input addresses increased and the capacity of the ROM became large. For example, if the MH codeword is packed in 8-bit units, m
, n and l require 4.3 and 4 bits, respectively, then a total of 11 bits are required to represent variables input.
bits are required.

Furthermore, since ROM capacity and access time are generally in a reciprocal relationship, the access time becomes longer as the ROM capacity increases.

Furthermore, when converting into an LSI, a problem arises in that it is difficult to implement if the ROM capacity is large.

Also, when decoding such an indefinite length code word packed into a constant pit length, a barrel shifter and a ROM sequencer are used as in encoding, but similar problems occur with this ROM sequencer.

The image encoding device of the present invention has been devised to solve the above-mentioned problems, and when speeding up the process of packing an indefinite length code word into units of an arbitrary number of bits, the image encoding device controls the packing control. The purpose is to reduce the number of address manpower by setting the number of ROM address inputs of the ROM sequencer to two variables.

Further, the image decoding device of the present invention aims to reduce the number of address manpower by selectively supplying a plurality of variables to the ROM address of a ROM sequencer that controls the decoding process.

[Means to solve the problem]

In order to achieve the above object, the present invention provides an image encoding device that packs an indefinite length code word encoded with image information into constant length data, including means for shifting the indefinite length code word by a plurality of bits at a time; A ROM for a sequencer that receives the code word length β of the indefinite length code word and a variable a indicating the packing processing state as an address input and determines the amount of shift in the bit shifting means; and a means for temporarily storing the code word in the bit position, and as a variable a indicating the packing processing state, bits already packed in the indefinite length code word are set from the number n of bits in which the code word has already been stored in the storing means. Particularly, the present invention provides an image decoding apparatus that uses a value obtained by subtracting a number m. , means for reading out the packed indefinite length code word in units of a fixed number of bits, means for shifting the data read out in units of the fixed number of pits by a plurality of bits at a time, and a code word length l of the indefinite length code word. Alternatively, a ROM for a sequencer to which a variable n indicating the conversion processing state is selectively supplied and determines the shift amount in the bit shifting means, and a ROM for temporarily storing the shifted data in an appropriate bit position and returning it to the original undefined length. The present invention is characterized in that it includes means for converting into a code word.

[Effect]

In the image encoding device of the present invention, instead of directly using a plurality of variables indicating the pack state necessary for encoding processing, the difference between the plurality of variables is calculated and used as a new variable.
This is the ROM sequencer's RO that controls the encoding process.
This is the input address of M. This reduces the number of input addresses to the ROM.

Furthermore, in the image encoding device of the present invention, a plurality of variables indicating the pack state necessary for encoding processing are not supplied in parallel to a ROM sequencer that controls decoding processing, but in a time-sharing manner. It is supplied by switching. Therefore, in this case as well, the number of input addresses to the ROM of the ROM sequencer is reduced.

〔Example〕

DETAILED DESCRIPTION OF THE INVENTION Hereinafter, features of the present invention will be specifically described based on examples with reference to the drawings.

First, the basic configuration of this embodiment will be explained with reference to the basic block diagram of FIG.

As shown in FIG. 1, the image encoding device of this embodiment includes a code generation circuit 1 that generates an indefinite length code word, and a process of packing the indefinite length code word into units of an arbitrary number of bits in units of multiple bits. unit bit packing means 2 consisting of a barrel shifter and a storage element, a memory 3 for storing code words packed into units of an arbitrary number of bits generated by the unit bit packing means 2, and a control sequencer 4 for controlling these. It is configured.

The control sequencer 4 is composed of a ROM sequencer whose address is the code word length and next processing control information, and is configured to perform a plurality of additions and subtractions in one cycle.

FIG. 2 is an explanatory diagram showing the packing state of an indefinite length code word in this embodiment. In the figure, l is the number of bits of the indefinite length code word, m is the number of already packed bits, and d is the bit to be packed. The number n indicates the number of bits in which the code word has already been stored. For example, in the following example, β is between 2 and 13, so it is expressed with 4 bits. Further, in this embodiment, (n-m) is expressed with 5 bits, with a being a.

If at least R and a of the variables R, m, d, and n shown in FIG. 2 are manually input to the address of the control sequencer 4,
As explained below, conversion processing can be performed without reducing processing speed.

FIG. 3 shows a block diagram of an image encoding device according to an embodiment of the present invention. In this embodiment, an example of an apparatus will be described in which an MH code of an undefined length code word with a code word length of 2 bits to 13 bits is packed in units of 8 pits and stored in a coding memory.

In the code generation circuit 5, the MH encoded result is divided into one code data of 16 bits and one code length data p of 4 bits per code (see (a) in the same figure) as shown in Fig. 4. 1 code is output in order (see (b) in the same figure), and a 20-bit F I F 0 (first-in-first
-outmemory) 6.

In other words, data r0000011 with a code of 12 pits
When it is 01001J, the code data is r00000
1101001XXXXJtonaF), the code length data l is rllooJ, that is, 12 in the lO base. Note that rXJ in the code data is a don't care bit regardless of the values of rOJ and m.

Note that when nothing is written to FIFO6, P
Empty flag EF is output from IFO6, and when FIFOll (described later) is full, FIF
It is assumed that a full flag FF is output from OIO.

Among the data written to FIFO6, the 16-bit code data rOO0001101001XXXXJ is
16-pit barrel shifter 7. Operated by 8-bit pit selector 8, code molecule 000001101001
Only J is extracted and stored in the 8-bit latch 9.

The other data is 4-bit code length data 1rl
100J is used for part of the address input of the ROM12.

As shown in FIG. 5(a), the ROM 12 has an empty flag εF and a full flag FF as address inputs.

It has a difference a between the number n of bits already stored in the code and the number m of bits already backed up, and the number l of bits of the indefinite length code. Further, as data output from the ROM 12, as shown in FIG. 5 (5), the difference a, the shift amount X in the barrel shifter 7, the selected position Y in the bit selector 8,
Clock flag CI for FIFO6, latch 9
A clock flag C2 for PIFOIO and a clock flag C3 for PIFOIO are provided.

The output of the ROM 12 is temporarily stored in a latch 13, from which the outputs X and Y are supplied to the barrel shifter 7 and pit selector 8, and the variable a is returned as the address input of the ROM 12. Further, among the outputs of the latch 13, the clock flags C1, C2, and C3 are supplied to a clock generation circuit 14, which generates a corresponding clock. In addition, R.O.
M12. The latch 13 and the clock generation circuit 14 constitute a ROM sequencer 15.

The barrel shifter 7 shifts the data to a specified force based on the input shift IX, and performs a left shift when X is positive, and performs a right shift when X is negative. Further, the pit selector 8 selects the human power of the latch 9 according to the human power Y, and the pit selector 8 selects the human power of the latch 9 according to the human power Y.
The output of the latch 9 is selected for pits up to the Y-th pit counting from 1ficant bit, and the output of the barrel shifter 7 is selected for pits below that.

Here, the 16 bits of code data are sequentially transferred to the barrel shifter 7.
, the process of being operated by the pit selector 8 and stored in the latch 9 will be explained with reference to the flowchart in FIG. 6 and the code example in FIG. Note that CKI, 2 for C, and 3 for C in the flowchart of FIG. 6 mean that reading from FIFO 6 and writing to latch 9 and FIFO lo are performed.

First, the states of each component such as the PIFO 6° barrel shifter 7 shown in the block diagram of FIG. 3 are initialized (step 101).

Now, data P as shown in FIG. 7(a) is stored in PIFO6.
L, P2. When P3 is written sequentially, data P1
When the empty flag l1iF is written, the process proceeds from step 102 to step 103, and the latch 9 enters the state of Ql in FIG. 7(b). That is, X
=o, y=o, so there is no shift in the barrel shifter 7, and the pit selector 8 selects only the output of the barrel shifter 7, so the first 16 bits of code data P1r011XXXXXXXXXXXXXJ(7)M
SB side 8-bit code data 01r011XXX
XXJ is written to latch 9.

Also, in the address manual of ROM12, a=0゜z=3
has been input, so a+β=3×8, and the process advances from step 104 to step 105. For convenience of explanation, it is assumed that the empty flag EF and the full flag FF are always cleared. Therefore, the next cycle goes to step 106 where a=a+1=3. X=-a
-1=-3, Y=a+1=3. In other words, the following 1
6-bit code data P2 [000011000xxx
xxxx'' Caharel shifter 7 is detected and shifted 3 bits to the right. Furthermore, since Y=3, the pit selector 8 outputs the upper 3 bits roll J of the data log 1r011XXXXXJ of the latch 9. Therefore, latch 9 is the seventh
The state of Q2 in Figure (b) becomes ro1100001J.

Further, the code length l of the second code data P2 is rlool
J, that is, 9 in lO base, and the address of the ROM 12 is a=3. Since f=9 is manually generated, a+
j! =12>8, so step 104.107.11
Proceed to 0. Therefore, the next cycle is step 111
Execute. That is, first, data r0110 (100IJ) of Q2 in FIG. 7(b) is written to the FIFOIO.

Also, since X=8-a=5, code data P2r0
00011000XXXXXXJ is shifted 5 bits to the left in barrel shifter 7 and becomes rrlOooXXXXXX
It becomes XXXXXXXJ. Further, since Y=Q, the bit selector 8 outputs only the output of the barrel shifter 7. Therefore, the latch 9 has the shape H "1000xxxx" in FIG. 7(b) (7) Q3.

Also, for the address input of the ROM 12, a=a-8=-
Since 5,1=9 is input, a+! =4×8, and in the next cycle step 106 is executed, and the latch 9 is in the state of Q4 in FIG. 7 (Company).

Also, in the address manual of ROM12, a=4゜1=1
2 has been input, so a+j7-=16>8, and in the next cycle, step 111 is executed and latch 9 is
The state becomes 05 in FIG. 7(b).

Also, for the address of ROM12, a=-4°! =
Since 12 has been input, a+f=8, and in the next cycle, step 109 is executed and data 05 of latch 9 (FIG. 7, etc.) is written to F IF 010.

In this way, specific length data is packed into 8-bit units one after another. As a result, the MH code, which is an indefinite length code having a code length of 2 bits to 13 bits, from the code generation circuit 5 is packed into 8-bit units and stored in the code memory 11.

Note that the above processing is performed in the ROM 12. The latch 13 and the clock generation circuit 14 execute the process based on the flowchart shown in FIG.

As described above, when performing high-speed pack processing using the barrel shifter 7, the ROM sequencer 15
Shift amount in barrel shifter 7.

The selection position of the pit selector 8 is calculated, and according to this embodiment, by introducing a new variable a, the number of addresses for the ROM sequencer 15 that performs pack control is changed from the conventional three variables to two variables. can be reduced to RO
The capacity of M12 can be reduced.

In other words, the address for the ROM 12 used to require 11 bits for the three variables m, n, and 1 shown in Figure 8(a), plus 2 bits for the empty flag EF and full flag FF, for a total of 13 pits. According to this embodiment, the number of bits can be reduced to 11 bits in total, consisting of 9 bits for two variables, the 5-bit variable a and the 4-bit variable l, and 2 bits for the flags EF and FF. Further, this reduction amount becomes larger as the values of the variables l and d become thicker.

Next, an example of an image decoding device that decodes the code generated by the above-described image encoding device will be described below.

First, the basic configuration of the image decoding device of this embodiment will be explained as follows.
This will be explained with reference to the basic block diagram shown in FIG.

In this embodiment, as shown in the figure, a memory 31 basically stores an indefinite length code word by packing it into units of an arbitrary number of bits.
and a unit bit processing means 32 consisting of a barrel shifter and a storage element for generating one indefinite length code word from the packed data and converting it into a form that matches the address input of the decoding table 33 in units of multiple bits. It is configured. In addition, a control sequencer 3 for controlling these
There are 4.

The control sequencer 34 is composed of a ROM sequencer and performs a plurality of additions and subtractions in one cycle.

FIGS. 11 and 12 are diagrams for explaining the process of processing an indefinite length code word packed in units of an arbitrary number of bits.

In FIG. 11, l is 4 bits β3~j! . The number of bits of the indefinite length code expressed as The number of stored bits, d indicates the number of bits to be packed, and e indicates the number of bits to be input into the decoding table 33. However, e must be larger than the maximum value that the number of pits l of an indefinite length code word can take.

In the ROM of the ROM sequencer, the number of bits of an indefinite length code word is 1. The number n of bits in which the code is stored is supplied, and based on these variables, the packed indefinite length codeword is converted into the original indefinite length codeword.

In this embodiment, a multiplexer 44 is provided before the ROM address input, and among the control variables shown in FIGS. 11 and 12, Il (4 pits of β col L) or n
(However, 4 pits out of 5 pits n4~no) ns~no)
By selecting and inputting one of the addresses, it is possible to reduce the amount of manpower required.

That is, as the address of the ROM, nl.

The portions R4, m2 to mO are commonly supplied, and in addition, either Tla to no or 13 to 1° is selectively supplied. Note that nl is a pit that controls switching of the multiplexer 44, and when n1=0, n3 to no
Choose a side, nj! When =1, l, ~β.

Choose a side.

The decoding table 33 has the maximum layer of the indefinite length code as the address input, and when a code shorter than the maximum layer is input, the code is input in order from the MSB of the address input section, and the pits below are accessed as don't care. be done. Also,
The decoded data from the decoding table 33 is the length of the indefinite length code! is also output.

An image decoding device according to an embodiment of the present invention will be explained according to the functional diagram of FIG. 13 and the flowchart of FIG. 14.

In this embodiment, data is read out in units of 8 pits from the code memory 35, which stores and packs MH-encoded indefinite-length codes with a code length of 2 bits to 13 bits.
An example of a device that inputs data into the decoding table 42 will be described. It is assumed that the decoding table 42 is accessed after the 16-bit code is stored in the latch 40.

In the code memory 35, indefinite length codes are stored in a packed form in 8-bit units as shown in FIG. will be held. Na right, 1st
Figure 5 (5) shows the form of the original long code.

Then, writing is performed from the code memory 35 to the FIFO 036, and the empty flag EF of the FIFO 36 is
When cleared, ROM sequencer 4 explained below
9 is activated, and the processing shown in the flowchart of FIG. 14 is executed.

First, each variable m, n, nl, X, Y is reset, and P
The contents of IFO 6 are read out (step 201). Note that X indicates the shift amount in the 16-bit barrel shifter 38, and a positive value is a left shift.

A negative value is a right shift. Also, Y is pit selector 3
Y bits from the MSB are taken from the latch 40 side, and the rest are taken from the barrel shifter 38 side.

Initially, since n=0, the process proceeds to steps 202 and 209, and the process of step 210 is performed. In the description here, it is assumed that the empty flag EF and the latch completion flag PG from the flagged latch 43, which will be described later, are both turned off. Further, it is assumed that the latch flag FG is cleared when the data in the flagged latch 43 is read from the outside.

Each variable in this case is m=Q, n=3. n1=0 (multiplexer 44 selects n, to n0 side).

X=0. Y=0. Furthermore, the three-state latch 37 is enabled by the data l1i1, and the three-state buffer 41 is disabled by the data E2. Furthermore, clock CK5. By CK6 and C7, F IF 036. Writing to the three-state latch 37 and latch 40 is performed.

As a result, the previously read data is latched into the three-state latch 37, and the barrel shifter 38. It passes through the pit selector 39 and is latched by the latch 40.

At this time, since x=0, there is no shift with the barrel shifter 38, and since Y=0, the pit selector 3
9 selects only the output of the barrel shifter 38. Therefore, the output of the latch 40 has a configuration as shown by R2 in FIG. That is, the 8 bits ro0000011J on the MSB side of the first 13-bit indefinite length code word ro000001110111J are selected, and the 16-bit output r
00000011fXXXXXXXj. In addition,
In the initial state, the data in the latch 40 is R1 in FIG.
As shown in , it is indeterminate.

Next, the next data from PIFO 6 is read out in the same manner as described above.

This time too, since n≠16, step 202゜2
09 and execute step 210. Each variable is m
=0. n=16. n1=0. When X=-8 and Y=8, the previously read data is latched by the latch 40 through the above route, becoming R3 in FIG. Also, the next data is read from the FIFO 6.

Next, since n=16 and n1=mouth, the process proceeds to steps 202 and 203, and step 204 is executed. Each variable is
m=o, n=16. nj! =1. When X=O, Y=0, the decoding table 42 is accessed by the data stored in the latch 40 in the previous cycle (R3 in FIG. 16), so the flagged latch 43 stores the decoding result and the indefinite length code. The length l of is stored.

Next, without reading data from PIFO6, latch 40
The output is output as is as R4 in FIG.

Next is nj! =l is manually input to the multiplexer 44, so the 4 bits ft3 to Ilo side of β are selected instead of the lower 4 bits n3 to no side of n. Also, since m=0, step 206 is executed and m=Q.

n=16-13=3. nj! =0 (output of multiplexer 44 changes from 1 to n), X=13. When Y=O, the three-state buffer 41 is enabled, and the latch 40 latches data such as R5 in FIG.

Next, since n≠16, step 210 is executed again, m=Q, n=11. n1=0. X=-3, Y=3, the three-steed raft 37 is enabled again, and the data like R6 in FIG. 16 is latched into the latch 40. Further, the following data is read from the FIFO 36.

Next, since n≠16, step 210 is executed again,
m=5. n=1(i, nj!=O, X=-11, Y=1
1, and the latch 40 latches data such as R7 in FIG. Further, the following data is read from the FIFO 6.

Next, since n=16, step 204 is executed and m
=5. n=16. nR=lX=0. Y=O,
Since the decoding table 42 has been accessed by the data stored in the latch 40 in the previous cycle, the decoding result and the length of the indefinite length code are stored in the latch with flag 43.

Next time too! Since =l is input to the multiplexer 44, the fls~L side is selected instead of the 13~no side. Also, since m≠0, step 207 is executed and m
=5. m=o, n1=1. X=5. When Y=0, the three-state buffer 41 is enabled.
Data such as R6 in FIG. 16 is latched.

Next, execute step 208, m=Q, n=14゜n
1=0. Three-state latch 3 with X=-6, Y=11
7 is enabled, and the output of the latch 40 becomes like R9 in FIG.

Next, since n≠16, execute step 210 and m=2
．． n=16. n1=o, X=-14, Y=14,
Data such as RIO in FIG. 16 is latched into the latch 40. Further, the following data is read from the PIFO6.

Note that in the RIO data in FIG. 16, there is an undefined pit value of 1:2 (=16-14) from the latch 40, so new data is added from FIFO 6 with 2 bits and R11 in FIG. The data shown in

Such operations are repeated to decode one page.

Here, FIG. 17 shows the address input and data output of the ROM2S in this embodiment. In addition, the conventional method R
FIG. 18 shows the address input and data output of OM.

In the case of reading and decoding a packed MH code in units of 8 bits according to the specifications of this embodiment, in the conventional method, the address input is 5 bits for n, 3 bits for m, and 4 bits for l.

The flags EF and FG are 2 bits, a total of 14 bits.

On the other hand, in this embodiment, the address input is n.

and 5 bits of n3 to n0 or 13 to 10, 3 bits of m, 1 bit of the switching signal of the multiplexer 44, and 2 bits of flags EF and FG, reducing the total to 11 bits. In other words, since the number of bits decreases by 3, the ROM capacity becomes approximately 8.
(It turns out that =23>1/1.

As mentioned above, in the image decoding device of this embodiment,
When converting an undefined length code backed by an arbitrary number of bits to the original undefined length code, the number of addresses in the ROM 2S is reduced by switching and using the address input of the ROM 45 that controls the barrel shifter 38 for pit processing. can do.

In the above embodiment, the image encoding device and the image decoding device were described as independent devices, but the image encoding device and the image decoding device can be made the same by sharing the circuit configuration and changing the connections. can be used. For example, the FIFO6 shown in the image encoding device of FIG.
Barrel shifter 7, bit selector 8. Latch9. The code memory 11° ROM2R, latch 13, and clock generation circuit 14 are connected to the FI circuit shown in the image decoding device of FIG.
F 036° Barrel Shifter 38. Bit selector 39
．． Latch 40° code memory 35. ROM2S,
Latch 46. It can be shared in correspondence with the clock generation circuit 47. However, in this case, some items can be completely shared, while others can only partially be shared.

Also, in place of the ROM12.45 in the above embodiment, the PL
A microprogram control logic IC such as A (programmable logic array) can also be used as a sequencer.

〔Effect of the invention〕

The image encoding device of the present invention packs an indefinite length code into a constant length code using a means for shifting multiple bits of the indefinite length code at once, such as a barrel shifter. RO calculates the required shift amount, etc.
This is done by M.

Here, instead of directly inputting a plurality of variables manually as an address for this ROM, the difference between the variables is input as a new variable, so the number of addresses is reduced.

Therefore, the capacity of the ROM can be reduced and the operation speed can be increased. Furthermore, since the capacity of the ROM can be reduced, it can be easily integrated into an LSI.

In addition, the image naturalization device of the present invention uses a barrel shifter or the like to convert an indefinite length code packed into a fixed number of bits into an indefinite length code table into a form that can be performed manually.
A switching means is provided in front of the ROM address input that controls the barrel shifter, and a plurality of variables are selectively supplied to the ROM.

This reduces the number of address inputs and greatly reduces the ROM capacity. Therefore, it is possible to increase the speed and easily implement it into an LSI.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of the image encoding device of the present invention, FIG. 2 is an explanatory diagram of variables used in the ROM of the image encoding device, and FIG. 3 is an image code of the embodiment of the present invention. FIG. 4 is an explanatory diagram showing the relationship between the code itself, code data, and code length data; FIG. 5 is an explanatory diagram showing the relationship between address input and data output of the ROM of this embodiment; 6 is a flowchart for explaining the operation of the image encoding device shown in FIG. 3, FIG. 7 is an explanatory diagram showing the process of packing code data of an indefinite length code word into a fixed length,
The figure is an explanatory diagram comparing the number of address inputs in the conventional example and the number of address inputs in this embodiment, and FIG. 9 is a block diagram showing an example of the configuration of a conventional image encoding device. FIG. 10 is a block diagram showing the basic configuration of the image decoding device of the present invention.
Fig. 1 is an explanatory diagram of variables used in the ROM of the image decoding device, Fig. 12 is an explanatory diagram showing switching of input addresses of the ROM, and Fig. 13 is a block diagram of the image decoding device according to the embodiment of the present invention. 14 is a flowchart for explaining the operation of the image decoding device shown in FIG.
5 is an explanatory diagram showing the relationship between packed data and indefinite length codes, FIG. 16 is an explanatory diagram showing input data to the decoding table and the values of each control parameter at each step in this embodiment, Figure 17 is an explanatory diagram showing the relationship between ROM address input and data output in this embodiment;
The figure is an explanatory diagram showing the relationship between address input and data output of a ROM in a conventional example. 1.5, 20: Code generation circuit 2: Unit bit pack means 3.31: Memory 4.34: Control sequencer 6.10.36: FIFO-7, aa: Barrel shifter 8.39: Bit selector 9.13.40 .4
6: Latch 11, 23.35: Code memory 12.4
5: ROM14.47: Clock generation circuit 15.49
F ROM sequencer 21゜22: Shift register 3
2: Unit bit processing means 33. 42: Decoding table 37: Three-state latch 41 Three-state buffer 43: Latch with flag 44: Multiplexer 48
: Read/write control circuit patent applicant Fuji Xerox Co., Ltd. Agent Masu Kobori (and 2 others) Address input (b) Data output 1) Data in memory (b) T constant &'t!

Claims (1)

[Scope of Claims] 1. In an image encoding device that packs an indefinite length code word encoded with image information into constant length data, means for shifting the indefinite length code word by a plurality of bits at a time, and the indefinite length code a ROM for a sequencer that takes a variable a indicating the code word length l of a word and a packing processing state as an address input and determines the amount of shift in the bit shifting means; as a variable a indicating the pack processing state;
the number n of bits in which the code word has already been stored in the storage means;
An image encoding device characterized in that a value obtained by subtracting the number m of bits already packed in the indefinite length code word from is used. 2. In an image decoding device that converts an undefined length code word packed into constant length data into the original undefined length code word and then decodes the same, a means for reading out the packed undefined length code word in units of a constant number of bits; means for shifting the data read out in units of a certain number of bits by a plurality of bits at a time; and means for selectively supplying the variable n indicating the code word length l of the indefinite length code word or the conversion processing state and shifting the bits. An image decoding device comprising: a ROM for a sequencer that determines the amount of shift in the data; and means for temporarily storing the shifted data in an appropriate bit position and converting it into the original indefinite length code word. .