JPH0284950U

JPH0284950U -

Info

Publication number: JPH0284950U
Application number: JP16327688U
Authority: JP
Priority date: 1988-12-16
Filing date: 1988-12-16
Publication date: 1990-07-03

Description

[Brief explanation of drawings]

第１図は本考案に係るインターフエース回路の
構成例とボードテスタ及びＤＵＴとの接続を示す
図、第２図はタイミング回路８の具体的構成例を
示す図、第３図は第１図のタイムチヤートである
。８……タイミング回路、１６……ゲート、１７
……ラツチ、３０……インターフエース回路。 FIG. 1 is a diagram showing a configuration example of an interface circuit according to the present invention and its connection with a board tester and a DUT, FIG. 2 is a diagram showing a specific configuration example of a timing circuit 8, and FIG. It is a time chart. 8...Timing circuit, 16...Gate, 17
...Latch, 30...Interface circuit.

Claims

[Claim for Utility Model Registration] Sending a write/read signal (R/), an address signal, and an address strobe signal () from a board tester to a logic board under test,
In a system in which the logic board under test performs a data write or read operation when the address strobe signal becomes active, and data is transmitted in both directions, a gate means 16 for controlling the passage of data output from the board tester side is used. , a means 17 for temporarily holding the data output from the logic board under test, and a means 17 for receiving a signal from the board tester and applying an address strobe signal ( An interface circuit comprising: a timing circuit for applying a latch signal to the means 17 to control the holding timing;