JPH0196041U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the test device according to the present invention, FIG. 2 is a diagram showing the operation flow and memory contents of the device shown in FIG. 1, and FIGS. 3 and 4 are diagrams showing a conventional example. It is. 1...System controller, 2...Latch circuit,
3... Multiplexer, 4... Memory, 5... Timing circuit, 10, 20... Module controller.

Claims (1)

[Claims for Utility Model Registration] A system controller, a plurality of measurement modules that transmit and receive various signals to and from the DUT, and a sequence number output from the system controller (an upper-order number of a setting data table stored in advance in memory, which will be described later). A latch circuit 2 stores a number corresponding to an address), a timing circuit outputs a setting timing signal, and a plurality of setting data tables are stored in advance, each consisting of a series of setting data that causes the measurement module to be controlled to perform a predetermined operation. and a memory whose contents are read out, with the output of the latch circuit as an upper address and the output signal of the timing circuit as a lower address, and a memory whose contents are read out.