JPH0286213A - analog switch circuit - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an analog switch circuit,
S Caused by the parasitic capacitance of the transistor.

This invention relates to an analog switch that uses a differential amplifier and a diode to control the gate voltage of a MOS transistor in order to reduce feed-through noise.

BACKGROUND OF THE INVENTION Analog switch circuits provide high-speed switching characteristics and are widely used as switching means in electronic circuits.

Bipolar transistors and MOS transistors are used as active elements in analog switch circuits, but since bipolar switches have an offset voltage, switches made of MO8 transistors have become popular in recent years.

FIG. 4 is a circuit diagram showing an example of a conventional analog switch circuit. In FIG. 4, a P-channel transistor 4 whose source is connected to a signal input terminal 6, whose gate is connected to a two-stage inverter 2, whose drain is grounded via a capacitor 8, and whose drain is connected to an output terminal 7, The operation of an analog switch circuit consisting of an N-channel transistor 5 connected to a signal input terminal 6, a gate connected to an inverter, a source grounded via a capacitor 8, and an output terminal 7 will be described below. Explain. First, when the control signal terminal 1 is at a low level "L", the "L" control signal terminal 1 is applied to the gate of the P-channel transistor 4 via the two-stage inverter 2, and the P-channel transistor 4 is turned on.

Also, when the control signal terminal 1 is "L", the control signal l of H is applied to the gate of the N-channel transistor 5 via the inverter 3.
is applied, and the N-channel transistor turns on. P
When the channel transistor 4 and the N-channel transistor 5 are turned on, when an input signal is input from the signal input terminal 6, the electric image corresponding to the voltage value of the input signal is stored in the capacitor 8, and the output terminal 7 receives the input signal. The voltage value will be the same as that of Next, when the control signal terminal 1 is at a high level "H-", the clock control signal 1 at "H" is applied to the gate of the P-channel transistor 4 via the two-stage inverter 2, and the P-channel transistor 4 is turned off. When control signal 1 is H, control signal 1 of "L" is applied to the gate of N-channel transistor 5 via inverter 3, and N-channel transistor 5 is turned off. P-channel transistor 4 and N-channel transistor 5 are turned off. Then, the signal input terminal 6 is disconnected from the output terminal 7, and the voltage of the input signal at the moment of turning from on to off is connected to the capacitor 8.

Problems to be Solved by the Invention However, as shown in FIG. 2, a MOS transistor has parasitic capacitances COS and COO between the gate and source and between the gate and drain. Therefore, when the switch is turned on and off, a control signal flows from the gate to the source and drain, causing an error voltage ve due to feed-through noise to the voltage of the input signal held in the capacitor at the moment of turning from on to off.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide an analog switch circuit that reduces the error voltage generated when switching control signals.

Means for Solving the Problems To achieve this object, the present invention provides a method in which the source is connected to the signal input terminal, the gate is connected to the anode of the first diode, and the non-inverting input of the first differential amplifier is connected to the input terminal of the first diode. a first P-channel transistor connected to the terminal, a drain connected to the signal input terminal, a gate connected to the cathode of the second diode, and a source connected to the train of the first P-channel transistor; First N
A circuit in which a channel transistor and an output of the first differential amplifier are connected to a cathode of the first diode and an anode of the second diode, and further connected to an inverting input terminal of the first differential amplifier. It is an analog switch.

Effect: With this configuration, the voltage value of the control signal can be made constant with respect to the voltage value of the signal input in order to reduce the error voltage that occurs when the control signal is switched. It is possible to reduce feedthrough noise due to intervening capacitance.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a MOS analog switch in one embodiment of the present invention. In FIG. 1, the source is connected to the signal input terminal 6, and the gate is connected to the diode 1.
0, is connected to the control signal terminal l via the two-stage inverter 2, has its drain grounded via the capacitor 8, and is further connected to the non-inverting input terminal of the differential amplifier 9. P-channel transistor 4 and its drain are connected to signal input terminal 6, its gate is connected to the cathode of diode 11, and further connected to the output of inverter 3, and its source is connected to P-channel transistor 4.
, and further connected to the non-inverting input terminal of the differential amplifier 9. N-channel transistor5. ! =
, the output of the first differential amplifier is connected to the cathode of the diode 10 and the anode of the diode 11, and further connected to the inverting input terminal of the differential amplifier 9.

First, when the control signal terminal 1 is "L", the "L" clock control signal terminal 1 is applied to the gate of the P-channel transistor 4 via the two-stage inverter 2, and the P-channel transistor 4 is turned on. Control signal 1 is “L”
N-channel transistor 5 via inverter 3 when
A control signal l of "I(" is applied to the gate of , and the N-channel transistor 5 is turned on. When the P-channel transistor 4 and the N-channel transistor 5 are turned on, a charge is applied to the capacitor 8 according to the voltage value of the signal input terminal 6. is stored, and the voltage value of the input signal is output to the output terminal 7.The voltage value of the input signal output to the output terminal 7 is input to the non-inverting input terminal of the differential amplifier 9, and is output. but,
Diodes 10 and 11 are reverse biased, so they do not turn on, and P-channel transistors 4. The gate voltage value of N-channel transistor 5 does not change.

Next, when the control signal terminal 1 is at the H level, the gate of the P-channel transistor 4 is connected to the H level via the two-stage inverter 2.
When the control signal 1 of ゛ is "H", °F is applied to the gate of the P-channel transistor 4 via the two-stage inverter 2.
1" control signal is applied, and the P-channel transistor 4 is turned off. Also, when the control signal is "H", a "L" signal is applied to the gate of the N-channel transistor 5 via the inverter 3.
When the N-channel transistor 5 is turned off by applying a control signal of
The capacitor S holds the voltage value of the input signal 6 at the moment the switch is turned off from on. The voltage value of the output terminal 7 is outputted via the differential amplifier 9. At this time, the voltage value of the output terminal 7 is outputted from the diode 10.
11 is turned on, the gate of the P-channel transistor 4 becomes a voltage higher than the voltage value of the output terminal 7 by 0.7 V (VBE). On the other hand, the gate voltage of the N-channel transistor 5 becomes a voltage lower than the voltage value of the output terminal 7 by 0.7 V (VBE). That is, when the P-channel transistor 4 is turned off, the voltage difference between the gate and the drain and source has a constant relationship of 0.7V, which is the voltage value of the input signal 6, regardless of the input signal 6. Further, when the N-channel transistor 5 is turned off, the voltage difference between the gate and the drain and source has a constant relationship of 7V, which is the voltage value of the human input signal 6. In other words, the magnitude of feedthrough noise generated by the control signal flowing from the gate to the source and drain during on and off times is constant regardless of the voltage value of the input signal.

As described in detail, according to the present invention, the voltage value of the input signal 6 outputted to the output terminal 7 is outputted via the differential amplifier 9, and the signal 6 is outputted via the diode 10°11. By feeding back to the gates of the P-channel transistor 4 and N-channel transistor 5 and controlling the gate voltages of the P-channel transistor 4 and N-channel transistor 5, when the MOS transistor is turned from on to off, the control signal 1 is used to control the voltage from the gate. Feedthrough noise is reduced through the parasitic capacitance of the source and drain, and a high-speed switch circuit can be realized, which has a great practical effect.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a MOS analog switch circuit in the first embodiment of the present invention, Fig. 2 is an equivalent circuit diagram showing the parasitic capacitance of a MOS transistor, and Fig. 3 is an electrical waveform at the second output terminal Vo. 4 are circuit diagrams of conventional MOS analog switch circuits. 1...Control signal, 2...Inverter circuit consisting of two stages, 3...Inverter circuit, 4...
...P channel transistor, 5...
N-channel transistor, 6...signal input terminal, 7...output terminal, 8...capacitor, 9...differential amplifier, 10.11...・・・
... Diode, 12 ... Parasitic capacitance between gate and source, 13 ... Parasitic capacitance between gate and drain, 14 ... Input terminal, 15 ... Output Voltage. /-111T m Is No. 2・-2#2 Nora rj Inbound 3-・Imperg 4-F Tame tag transisg 5゛°°～°°～Te Misaki Nsisig 6...-Signal input O7-・Output range 1 child 8・-Huntenbu q'-Balance 1 chanting ro, n =-Guiod diagram Figure 3/Z-Kate source inter-source deafness M, quantity 13- Gate-drain parasitic, calculation . 14°-°Rokuryoku Electric 5f5--Output Electrical Works

Claims (1)

[Claims] The source is connected to the first signal input terminal, and the gate is connected to the first signal input terminal.
connected to the control terminal of the first diode and the anode of the first diode;
a first capacitor whose drain is grounded via the first capacitor and further connected to the non-inverting input terminal of the first differential amplifier;
a P-channel transistor with a drain connected to the first signal input terminal, a gate connected to a second control terminal and a cathode of the second diode, and a source connected to the drain of the first P-channel transistor. is,
The output of the first differential amplifier is connected to the cathode of the first diode and the anode of the second diode, and further connected to the inverting input terminal of the first differential amplifier. analog switch circuit.