JPH0286318A - Level converting circuit - Google Patents

Abstract

PURPOSE:To make the logic level stable and to suppress the production of a DC current by providing a P-channel MOSFET to a base of an emitter follower output transistor(TR) and an N-channel MOSFET to the emitter in a differential TR circuit. CONSTITUTION:An input signal is given to a gate of P-channel MOSFETs Q1, Q3 and a gate of N-channel MOSFETs Q2, Q4 with a level difference by a voltage drop of resistors R3, R4 and a hase-emitter voltage VBE of TRs T3, T4 with respect to an output signal of a differential TR circuit. Thus, even when an ECL level to be level-converted is at a midpoint potential, the conductance of the FETs Q1, Q3 and the FETs Q2, Q4 is comparatively decreased. Then a DC current flowing through the FETs Q1, Q2 and Q3, Q4 is limited. Since the ratio of the conductance of the FET Q1 turned on at a low level is adopted larger, the stability of the operation is attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a level conversion circuit, and particularly to a level conversion circuit that is used to convert an ECL (emitter coupled logic) signal to a 0MO3 (complementary MO3) level. It is about effective techniques.

[Conventional technology]

Faster operation due to the use of bipolar transistors and lower power consumption due to the use of the 0M03 circuit.
There is a Bi-CMO8 circuit that has achieved high integration. As an example of the i-0M03 circuit, February 1, 1982
2nd “Inis Nisshi Sea ‘82 Sera’/a7X
"1 JPP, 24B-249 (I 5SCC'82 5
ESSION

[Problem to be solved by the invention]

In the Bi-0M03 circuit, when the ECL circuit and 0M03 circuit are combined, the ECL level signal is
A level conversion circuit is required to convert the signal to an S level signal. As such a level conversion circuit, it is possible to level shift an ECL level signal via an emitter follower output circuit and form a signal that becomes high level and low level relative to the logic threshold voltage of the CMOS inverter circuit. Conceivable.

However, in this case, the logic threshold voltage of the CMOS inverter circuit is
Since there is a relatively large variation depending on the conductance ratio between the 3FET and the N-channel MOSFET, the operation becomes unstable. Furthermore, since the signal amplitude of the ECL level is relatively small, the P-channel MO8FET or N-channel MOSFET cannot be completely turned off even at the high/low level, resulting in the problem that DC current flows through both MO3FETs. .

An object of the present invention is to provide a level conversion circuit that has a simple configuration and achieves stable operation and low power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a differential transistor circuit receiving an ECL level input signal, its emitter follower output transistor, and a first conductivity type MOS F constituting a CMOS output circuit whose gates are commonly connected to the bases of the transistors.
ET and a second conductivity type M constituting a CMOS output circuit that receives an output signal on the emitter side of the output transistor.
OS FET is provided.

[For production]

According to the above-mentioned means, since the driving voltage supplied to the gates of the P-channel MOSFET and N-channel MOSFET constituting the 0M03 circuit is offset by at least the voltage between the base and emitter of the output transistor, the The logic level can be stabilized,
Moreover, generation of direct current can be suppressed.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment of a level conversion circuit according to the present invention. Each circuit element in the figure is formed on a single semiconductor substrate, such as, but not limited to, single crystal silicon, using known Bi-CMOS circuit technology.

A complementary signal dl formed by an ECL circuit (not shown) is applied to the bases of the differential transistors T1 and T2.

di is supplied. A constant current source 1o is provided at the common emitter of these transistors T1 and T2. A load resistor R1 is installed on the collector side of the transistors T1 and T2.
, R2 are provided.

The collector output signals of the transistors TI and T2 are respectively connected to the base of the emitter follower output transistor T3.74 and the P channel M which constitutes the CMOS output circuit.
Supplied to the gates of O3FETQI and Q3. In other words, the emitter follower output transistors T3 and T
The base of P-channel MOS FETQ 4 and the gates of P-channel MOS FETQ 1 and Q3 are connected in common.

The emitters of the output transistors T3 and T4 are connected in series with resistors R3 and R4 for level shifting, and a constant current source IO through which an operating current flows, although this is not particularly limited. The level shift amount is set according to the resistance values of the resistors R3 and R4 and the constant current value of the constant current source Io flowing thereto. The output signal via the level shift resistors R3 and R4 is supplied to the gates of N-channel MO3FETs Q2 and Q4, which constitute a CMOS circuit output circuit connected in series with the P-channel MO3FETs QI and Q3, respectively.

P-channel MO3F that constitutes the above CMOS output circuit
ETQI, Q3 and N-channel MO3FETQ2 and Q4
Output signals d'o and do converted to CMOS level are obtained from the respective connection points of .

The ECL circuit in this embodiment has a different operating voltage from a normal ECL circuit. That is, in a normal ECL circuit, the voltage on the high level side is set to the ground potential, and the voltage is -5.2V.
Use a negative polarity voltage such as . On the other hand, in the ECL circuit in this embodiment, the voltage on the high level side is approximately 5
The power supply voltage Vcc is set as follows, and the ground potential is used as the low-level voltage. This changes the operating voltage to normal CMO
This is due to the setting being made to match the S circuit side. The voltage v0 of the differential transistor circuit and emitter follower output circuit as the ECL side circuit is set to the ground potential of the circuit. Further, the low level side potential Vss on the CMOS circuit side is set to the ground potential of the circuit, and the above-mentioned power supply voltage Vcc is commonly used as the high level side voltage. Therefore, in the above configuration, the low level side potentials Vat and Vss of both circuits are connected in common.

Such a level conversion circuit can be used in a dynamic RAM using the differential circuit as a main amplifier. That is, the input signals di and di supplied to the differential transistor circuit are the read voltages of the dynamic memory cells that are transmitted to the common complementary data line (or the common input/output line).

In this case, when the constant current source IO of the differential transistor circuit is activated by the main amplifier operation timing signal, the sense amplifier that amplifies the minute signal on the complementary data line to which the memory cell is connected operates, and the column selection operation operates. After the complementary data lines are coupled to the common complementary data line, the amplification operation thereof is initiated.

When used in such a main amplifier, the input signals di and di cannot be said to be at ECL level in the strict sense, but by providing a level limiting circuit etc. on the common complementary data line, they can be regarded as ECL level. can. In this configuration, which limits the level amplitude of the common complementary data line, the relatively large parasitic capacitance on the common complementary data line can be charged/discharged at high speed. This enables high-speed operation.

In the level conversion circuit of the above embodiment, for the output signal of the differential transistor circuit, -P channel MO3FETQ
I, the gate of Q3 and the N-channel MO3FETQ2. Q
At the gate corresponding to transistor T3. The level difference (
The input signal is supplied with an offset). Therefore,
Even when the ECL level to be level-converted is at the midpoint potential, the P-channel MO3FET is
The conductance of QI, Q3 and N-channel MO8FETQ2, Q4 is relatively small (because both MO3FETQI
and limits the direct current flowing through Q2, Q3 and Q4. Therefore, for example, even when the input signal supplied to the base of the transistor T3 is at a low level, the gate of the N-channel MO3FET Q2 receives the voltage drop between the base and emitter voltage V) of the transistor T3 and the voltage drop across the resistor R3. As a result, a lower potential is supplied, and a state substantially close to an off state can be achieved. This makes it possible to increase the conductance ratio with the P-channel MO3FET QI, which is turned on by the low level, thereby stabilizing the operation.

This is true even when the input signal supplied to the base of the transistor T4 is at a low level.

Note that when the above input signal is at high level, the gate and source of P-channel MO3FET QI or Q3 are at V
Since the potential is the same as that of cc and completely turned off, a stable low level signal can be obtained.

[Embodiment 2] FIG. 2 shows a circuit diagram of another embodiment of the level conversion circuit according to the present invention.

In this embodiment, the differential transistor circuit constitutes an ECL circuit. That is, transistors TIO to Tln receiving a plurality of input signals diNdn are connected in parallel,
On the other hand, the transistor T receiving the reference voltage Vref
2 are provided in differential configuration. And load resistance R1 and R
2, a series diode DI as a level limiter,
D2 and D3. D4 is provided in parallel form. In this configuration, the low level output signal formed by the differential transistor circuit is transmitted to the operating constant current source 1o and the resistors R1 and R.
Regardless of the resistance value of the diode D1. D2 (
D3. D4) <7> Limited by forward voltage 2vy. This makes it possible to prevent saturation of the differential transistors and to perform high-speed current switching operations in the differential transistors. Note that the diodes DI to D4 are
It can be replaced by a diode-type transistor or a Schottky diode.

The differential transistor circuit may be an ECL circuit itself; however, in order to have a level conversion function, the emitter follower output circuit is added with level shifting means as described above. In this embodiment, forward diodes D5 and D6 are used as level shift means instead of the resistors R3 and R4 as described above. This diode D5. Needless to say, D6 may be a diode-type transistor.

N-channel MO3FETs Q5 and Q6 operate as constant current sources by supplying a constant voltage vG to their gates for series MOS FETs Q1, Q2, Q3, and Q4 that constitute a CMOS output circuit that performs level conversion operations.
are respectively provided in series.

In this embodiment as well, the differential transistor (
When the output signal of the ECL) circuit is at high level, P-channel MO3FETQI or Q3 is turned off and N-channel MOS FETQ2 or Q4 is turned on, so the corresponding CMOS output level is below the ground potential of the circuit. It becomes a low level like that. At this time, the above P
When channel MO3FETQI or Q3 is in the off state, no direct current flows, resulting in low power consumption.

Furthermore, when the above output signal is at a low level, the P-channel MO3FET Q1 or Q is turned on accordingly.
The conductance of 3 is set relatively large, and at that time, a lower potential that is further level-shifted from the above low level is set to N.
Supply it to channel MO3FET Q2 or Q4, and set its 0 conductance small. As a result, the conductance ratio becomes large, and a desired CMOS high level can be obtained quickly. Further, due to the above level shift effect, unnecessary direct current (leakage current) flowing through the N-channel MO3FET Q2 or Q4 can also be reduced.

The effects obtained from the above examples are as follows. That is, the emitter follower output transistor of the differential transistor circuit that receives an input signal of <11 E CL level, the P-channel M<)SFET constituting the CMOS output circuit whose gates are commonly connected to the bases, and the output transistor of the above output transistor. By providing an N-channel MOS FET that receives the output signal on the emitter side, at least the base of the output transistor.

Since the gate voltages of both MO3FETs are offset by the voltage between the emitters, the logic level can be stabilized by that amount, and the generation of direct current can be suppressed.

(2) The above TI) can significantly reduce unnecessary direct current, resulting in the effect of reducing power consumption.

(3) By providing an appropriate level shift means on the emitter side of the emitter follower output transistor and giving a larger offset voltage to the gate voltages of the P-channel MO3FET and N-channel MO3FET, it is possible to stabilize the operation and eliminate unnecessary The effect is that the leakage current can be significantly reduced.

(4) According to (1) or 3) above, the power supply voltage Vcc
The effect is that the operating margin against fluctuations in can be expanded.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. For example, for the operating voltage St voltage, a negative power supply voltage may be used, with the high level side potential set to the ground potential, in accordance with a normal ECL circuit. That is, in this configuration, the voltage Vcc in the embodiment circuits of FIGS. 1 and 2 is given the ground potential of the circuit, and is the voltage . A negative voltage such as -5.2 V or -5 V (7) is applied to Vss.

The level shift means may use a resistor and a constant current source as described above, a diode, or a diode-type MOSFET.

The present invention is applicable to semiconductor integrated circuit devices, etc. in which 0M08 circuits and bipolar transistor circuits coexist as a level conversion circuit that converts an input signal with a relatively small signal amplitude such as ECL to a large signal amplitude such as CMOS level. wide (something that can be used)

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, an emitter follower output transistor of a differential transistor circuit receiving an input signal at an ECL level;
By providing a P-channel MO3FET constituting a CMOS output circuit whose gates are commonly connected to their bases, and an N-channel MO3FET that receives an output signal on the emitter side of the output transistor, it is possible to reduce the voltage between at least the base and emitter of the output transistor. Only both MOS
Since an offset is provided to the gate voltage of the FET,
Accordingly, the logic level can be stabilized and the generation of direct current can be suppressed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the level conversion circuit according to the present invention, and FIG. 2 is a circuit diagram showing another embodiment of the level conversion circuit according to the present invention.

Claims (1)

[Claims] 1. A differential transistor circuit that receives an input signal at an ECL level, an emitter follower output transistor that receives an output signal of this differential transistor circuit, and a CMOS output whose gate is commonly connected to the base of the output transistor. It is characterized by comprising a first conductivity type MOSFET forming a circuit, and a second conductivity type MOSFET receiving an output signal on the emitter side of the output transistor and forming a CMOS output circuit together with the first conductivity type MOSFET. level conversion circuit. 2. The level conversion circuit according to claim 1, wherein the gate of the second conductivity type MOSFET is supplied with an emitter side output signal via level shift means. 3. The level conversion circuit according to claim 2, wherein the differential transistor circuit is provided with an output level limiter circuit.