JPH0286319A - Input/output circuit - Google Patents

Abstract

PURPOSE:To keep the potential at an input/output terminal when a potential higher or lower than the range of an operating power voltage of an internal circuit is applied externally by adopting the conduction type of the 3rd MOS transistor(TR) opposite to that of the 1st or 2nd MOS TR. CONSTITUTION:A source-drain connection of a depletion N-channel MOS TR 1 is inserted between an input output terminal 15 and a drain of a P-channel MOS TR 13. An internal signal S2 is supplied to a gate of the TR 1. When a potential higher than a power voltage Vcc of the internal circuit as a high level is applied to the input output terminal 15, the gate-source voltage of the TR 1 is negative and the TR 1 is turned off. Thus, a high level is kept at the input output terminal 15 and the high level fed to the input output terminal 15 is detected stably by a potential detection circuit 16.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) This invention relates to an input/output circuit built into a CMOS type semiconductor integrated circuit, and particularly relates to an input/output circuit built into a CMOS type semiconductor integrated circuit, and in particular to an input/output circuit that inputs/outputs signals. The present invention relates to an input/output circuit to which a signal potential higher than a power supply potential inside an output circuit or a signal potential lower than a reference potential inside an input/output circuit is supplied from an external circuit.

(Prior Art) In order to minimize the number of terminals in semiconductor devices such as CMOS type semiconductor integrated circuits, one terminal is often used for both signal input and signal output.

FIG. 4 is a circuit diagram showing the configuration of a conventional input/output circuit provided with input/output terminals for inputting and outputting signals as described above. This input/output circuit is provided in a peripheral circuit of a CMOS type semiconductor integrated circuit. In the figure, internal signals S1 and S
2 are both set to 'H' level, both signals S
The output of the NAND gate 11 to which L and S2 are input is II
L II level, inverted signal S of signal S1 and signal S2
The output of the NOR gate 12 to which 2 is input is also II L 1
1 level, P channel MOS transistor 1
8 is turned on, and the N-channel MOS transistor 14 is turned off. Therefore, at this time, the input/output terminal 15 outputs “H”.
The level signal is output to the outside. Next, when the internal signal S1 is set to "L" level and S2 is set to mHII level, the output of NAND gate 11 is set to 'H' level,
The output of the NOR gate 12 becomes "H" level, the P-channel MOS transistor 13 is turned off, and the N-channel MOS transistor 13 is turned off.
OS transistor 14 is turned on. At this time, an "L" level signal is output from the input/output terminal 15 to the outside.

Further, when the internal signal S2 is set to the "L" level, the output of the NAND gate 11 is set to the "H" level, the output of the NOR gate 12 is set to the 'L' level, and both the P channel and N channel transistors 13. 14 are both turned off. Therefore, at this time, the input/output terminal 15 becomes in a high impedance state, and it becomes possible to input a signal from the outside.

At this time, the potential level of the external signal input via the input/output terminal 15 is detected by the potential detection circuit 1B, and is supplied to the inside of the integrated circuit. This potential detection circuit 1G
is to detect a signal voltage higher than the power supply voltage,
For example, an inverter circuit is used.

FIG. 5 is a sectional view showing the element structure of the P-channel and N-channel MOS transistors 13 and 14 in the output stage in the conventional circuit. For example, the P-channel MOS transistor 13 is composed of a pair of P-type source write/drain diffusion regions 21 and 22 formed in an N-type substrate 20 and a gate structure 23 provided between them.
The channel MOS transistor 14 is composed of a pair of N type source φ drain diffusion regions 25 and 28 formed in a P well region 24 provided in an N type substrate 20 and a gate structure 27 provided therebetween. There is.

By the way, when applying a signal to the input/output terminal 15 from the outside, there is no problem if a signal having the same value as the power supply voltage VCC of the internal circuit is applied as the high potential. However, when a potential higher than vcc is applied and detected by the potential detection circuit 16, the high potential applied to the input/output terminal 15 causes damage between the P-type drain diffusion region 22 of the transistor 13 and the N-type substrate. 20 is a forward bias state. At this time, from the drain diffusion region 22 to the N type substrate 2
A current flows toward zero, and the high potential applied to the input/output terminal 15 decreases. As a result, not only is it impossible for the potential detection circuit 16 to detect a high potential, but there is a fear that the circuit may deteriorate and be destroyed. In addition, when a potential lower than the input/output terminal 151:Vss, that is, a negative potential is applied and this is detected by the potential detection circuit 1B, the P well region 24 and the N type drain diffusion region 2B During this time, a forward bias current is generated, and the negative low potential applied to the input/output terminal 15 rises.

(Problems to be Solved by the Invention) In this way, in conventional input/output circuits, a potential detection circuit, etc. is connected to the input/output terminal, and when a voltage outside the range of the power supply voltage of this circuit is applied from the outside, the input There is a problem in that current is generated in the terminals, which in the worst case can lead to circuit breakdown, and that voltage cannot be maintained at the input/output terminals, making it impossible to detect the potential.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to prevent the input/output terminals from turning off when a potential higher or lower than the operating power supply voltage range of the internal circuit is applied to the input/output terminals from the outside. It is an object of the present invention to provide an input/output circuit that can hold the potential at a constant voltage and stably detect the potential using the potential detection circuit 1.

[Structure of the invention] (Means for solving the problem) In the input/output circuit of this invention, one of the source and drain is the first
a first MOS transistor of a first conductivity type connected to a potential of , a second MOS transistor of a second conductivity type whose source or drain is connected to a second potential, and the first MOS transistor a third MOS transistor of a second conductivity type or a first conductivity type, the source and drain of which are connected to the other of the source and drain of the second MOS transistor; A connection point between one of the source and drain of the MOS transistor and the other of the source and drain of the first MOS transistor, or a connection point between the other of the source and drain of the third MOS transistor and the source and drain of the second MOS transistor. a signal input/output terminal connected to the connection point with the other; a means for generating a control signal to be supplied to the gates of each of the first, second, and third MOS transistors; and a signal input/output terminal connected to the signal input/output terminal. and a potential detection circuit that detects the signal potential supplied to this signal input/output terminal.

(Operation) Both the first and second MOS transistors are turned off, and the signal input terminal is set to a high impedance state. At this time, the normal power supply voltage is applied to the above terminals.

When a signal potential higher or lower than the range is applied, the conductivity type of the third MOS transistor is the opposite conductivity type to that of the first or second MOS transistor. The PN junction, in which one or the other of the source and drain of the MOS transistor is in a reverse bias state, is applied to the terminal and the signal potential is maintained as it is.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIG. 1 is a circuit diagram showing the structure of an embodiment of the human-powered refrigerant according to the present invention. Note that parts corresponding to those of the conventional circuit will be described with the same reference numerals. In this embodiment circuit, an input/output terminal 15 and a P-channel MOS transistor 13 are connected as shown in the figure.
M of the depletion type N-channel between the drain of
It is inserted between the source and drain of the OS transistor l. The gate of this transistor 1 is supplied with an internal signal S2.

In the figure, when both internal signals S1 and S2 are set to 'H' level, the output of the NAND gate 11 to which both signals Sl and S2 are input is 'L' level, and the inverted signal S2 of signals S1 and S2 is NOR gate, 1
The output of PMOS transistor 2 also becomes "L" level, P-channel MOS transistor 13 is turned on, and N-channel MOS transistor 14 is turned off.

At this time, since the transistor 1 is of the depletion type, the "H" level of the signal S2 is supplied to the gate, and when it is turned on, no voltage drop occurs between the source and drain. Therefore, at this time, an "H" level signal is output from the input/output terminal 15 to the outside.

Next, when the internal signal S1 is set to "L# level" and S2 is set to "H" level, the output of NAND gate 11 is set to "H" level.
” level, the output of the NOR gate 12 becomes 'H# level, the P-channel MOS transistor 13 turns off,
N-channel MOS transistor 14 is turned on. On the other hand, the transistor 1 whose gate is supplied with the "H" level of 82 is also in the on state, but at this time, the transistor 13 is off and the transistor 14 is on, so that the "L" level signal is sent from the input/output terminal 15. is output to the outside.

Furthermore, when the internal signal S2 is set to the "L" level, the output of the NAND gate 11 is set to the "H" level, the output of the NOR gate 12 is set to the "L" level, and both the P-channel and N-channel transistors 13 and 14 are Off together. Therefore, at this time, the input/output terminal 15 becomes in a high impedance state, and it becomes possible to input a signal from the outside. At this time, the potential level 1 of the external signal inputted through the input/output terminal 15 is detected by the potential detection circuit 16 and supplied to the inside of the integrated circuit.

FIG. 2 is a sectional view showing the device structure of the output stage P-channel and N-channel MOS transistors 11-14 and the depletion type N-channel MOS transistor 1 in the circuit shown in FIG. For example, P channel MOS
The transistor 18 is composed of a pair of P-type source/drain diffusion regions 21 and 22 formed in an N-type substrate 20 and a gate structure 23 provided between them. N-type substrate 20
A pair of N well regions 24 formed in
It consists of type source/drain diffusion regions 25, 28 and a gate structure 27 provided therebetween. The depletion type MOS transistor 1 consists of a pair of N-type source/drain diffusion regions 3.4 formed in the P-well region 2 provided in the N-type substrate 20 and a gate structure 5 provided therebetween. It is configured.

As described above, the operation of the circuit when the internal signal S2 is set to the "L" level and an external signal is input to the input/output terminal 15 will be described with reference to FIG. 8 at the gate
When “L” level of 2 is supplied, input/output terminal 1
When a high potential higher than the power supply voltage VCC of the internal circuit is applied to transistor 5, the potential between the gate and source of transistor 1 becomes a negative value, and transistor 1 is turned off. Moreover, since the PN junction between the N-type source diffusion region 3 and the P-well region 2 and the PN junction between the N-type drain diffusion region 2B and the P-well region 24 are in a reverse bias state, the input/output No leakage current occurs between terminal 15 and VCC. Therefore, a high potential is held at the input/output terminal 15, and the high potential applied to the input/output terminal 15 is stably detected by the potential detection circuit 1B in FIG.

In this way, a drop in potential due to a high potential leakage current of the input/output terminal 15 can be prevented. Also, S2 is “H”
When transistor 13 turns on at # level,
The VCC level must be transmitted to the input/output terminal 15. At this time, since no voltage drop occurs due to the depletion type transistor 1, VCC is applied to the input/output terminal 15.
level can be reliably communicated.

FIG. 3 is a circuit diagram showing a configuration according to another embodiment of the present invention. In the embodiment circuit shown in FIG. 1 above, the input/output terminal 15
By providing a depression type N-channel MOS transistor 1 between the input terminal 15 and the drain of the transistor 13, a potential drop is prevented when a positive high potential is applied to the input/output terminal 15. In contrast, in this embodiment circuit, a depletion type P-channel MOS transistor 6 is provided between the input/output terminal 15 and the drain of the transistor 14 as shown in the figure, so that the input/output terminal 15 has a voltage lower than the ground voltage VSS. This is to prevent the potential from increasing when a voltage of negative polarity is applied. As a result, the low voltage at the input/output terminal 15 is maintained stably, and detection by the potential detection circuit 16 becomes possible.

Furthermore, in normal operation, when the transistor 14 is turned on and outputs the "L" level to the input/output terminal 15, as in the circuit shown in FIG. Since no drop occurs, the potential of the input/output terminal 15 can be set to L'' level.

[Effects of the Invention] As explained above, according to the present invention, when a potential higher or lower than the operating power supply voltage range of the internal circuit is applied from the outside, that potential can be held at the input/output terminal, and the potential can be detected. An input/output circuit that can stably detect the circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a configuration according to an embodiment of the present invention;
FIG. 2 is an equivalent circuit diagram showing a partial configuration of the circuit in FIG. 1 in a cross-sectional view, FIG. 3 is a circuit diagram showing the configuration of another embodiment of the present invention, and FIG. 4 is a diagram of a conventional input/output circuit. FIG. 5 is an equivalent circuit diagram showing a partial configuration of the circuit of FIG. 4 in a cross-sectional view. DESCRIPTION OF SYMBOLS 1... Depression type N channel MOS transistor, 11... NAND gate, 12... NOR gate, 13... P channel MOS transistor, 14
...N channel MOS transistor, 15...input/output terminal, 1B...potential detection circuit. Figure Figure

Claims (3)

[Claims] (1) A first MOS transistor of a first conductivity type with one of its source and drain connected to a first potential;
a second MOS transistor of a second conductivity type, one of whose drains is connected to a second potential; the other of the source and drain of the first MOS transistor; and the other of the source and drain of the second MOS transistor; a third MOS transistor of the second conductivity type or the first conductivity type, the source and drain of which are connected, and one of the source and drain of the third MOS transistor and the source and drain of the first MOS transistor; a signal input/output terminal connected to a connection point with the other MOS transistor or a connection point between the other of the source and drain of the third MOS transistor and the other of the source and drain of the second MOS transistor; An input/output circuit comprising means for generating a control signal to be supplied to the gates of each of the second and third MOS transistors. (2) The input/output circuit according to claim 1, wherein the first and second transistors are of an enhancement type, and the third transistor is of a depletion type. (3) The input/output circuit according to claim 1, further comprising a potential detection circuit connected to the signal input/output terminal and detecting a signal potential supplied to the signal input/output terminal.