JPH0287257A - data processing equipment - Google Patents

Abstract

PURPOSE:To improve data transfer efficiency by providing the data buffer of a first in first out (FIFO) system which is connected to an external data bus and execute data transfer with another data processor. CONSTITUTION:In a single chip microcomputer, two FIFOs 3 and 4 for data input and output and a FIFO status register 5, which shows the data housing condition of the FIFOs 3 and 4, are provided. Thus, it is informed in correspondence to the contents of the status register 5 that there is the transferring of data interruption to the external processor or the exterminal and internal processors. Accordingly, when the data are transferred between two multi- processors which are mutually connected, it is not necessary to once house the data in an internal ROM 7 and the data can be continuously sent until the FIFOs 3 and 4 are filled up without waiting the processing of the other processor. Thus, the data transfer efficiency is improved and the through-put of a system can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing technology and a technology that is particularly effective when applied to a data transfer method of a single-chip microcomputer. This book concerns technology that is effective for use in single-chip microcontrollers such as those used as microcontrollers.

[Prior Art] In a microcomputer system such as a personal computer, the microcomputer r, SI is
One system may be constructed using two or more microprocessors, such as when used as a controller for a computer. In this case, - for boat fishing, one processor is used as a master processor, and the other processor is used as an auxiliary slave processor.

For example, in a system having two microcomputers such as Japanese Patent Application Laid-Open No. 60-027030.

Transfer is required between the mask side and slave side microcomputers.

[Problems to be Solved by the Invention] Conventionally provided microcomputer LSIs do not give sufficient consideration to processing efficiency when operating as a slave processor. For example, when a slave processor processes data sent from a master processor, When outputting from the I10 port, if the transfer speed of the I10 port is slow, the slave processor needs to temporarily store the data sent from the master processor in its internal RAM. Since this processing is performed by program execution by the slave processor, it takes time to take in the data, resulting in the mask processor being kept waiting. To prevent this, there is a method of notifying the mask processor using an interrupt, but in this case, interrupt processing time occurs as overhead. On the other hand, when data from D/O is sent to the mask processor, data may be dropped if the data transfer from Ilo is fast.

Therefore, in order to enable high-speed data transfer between two processors, a single-chip microcomputer with a built-in parallel communication interface circuit with dual-port RAM has been proposed (Hitachi, Ltd.). Seisakusho, published September 1985,
(See "Hitachi Microcomputer Data Book 8-bit Single Chip," pages 787 to 789).

However, in the single-chip microcomputer with a built-in dual-port RAM, it is necessary to constantly monitor whether data has been written to the dual-port RAM and to avoid access conflicts.

In addition, dual port RA is used to increase the amount of communication at one time.
If the capacity of M is increased, there is an inconvenience that the dual baud 1-RAM area occupies a large proportion of the address space of the microcomputer.

An object of the present invention is to provide a single-chip microcomputer that can improve the efficiency of data transfer between microprocessors in a multiprocessor system by simply adding hardware.

The above and other objects and novel features of the present invention will become clear from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, two first-in/first-out memories (hereinafter referred to as FIFO) for data input/output, and a FIFO that indicates the data storage status of the FIFO.
A status register is provided, and depending on the contents of the status register, an interrupt is used to notify the external or external and internal processors that data has been transferred.

[Operation] According to the above-described means, when data is transferred between two multiprocessors connected to each other, the internal R
Since there is no need to store data in AM, it is possible to continue sending data until the FIFO is full without waiting for processing by the other processor.

In addition, since the processor is automatically notified when the FIFO becomes full, there is no need to constantly monitor whether data has been transferred or not, and it is also possible to know the data storage status in the FIFO by reading the FIF○ status register. Can be done.

[Example] An embodiment of the present invention will be described below with reference to FIG.

The main CPU 15 entrusts the functions of controlling the external T/○ device 18 and transmitting and receiving data to the single-chip microcomputer 1, and the single-chip microcomputer 1 operates as an I10 controller. The single-chip microcomputer 1 has a local CPU 2, RAM 7.
ROM8. Timer 9. Serial communication interface (hereinafter abbreviated as SCI) 10. Each of these functional blocks is connected to each other by an internal bus 12.

In this embodiment, in addition to the above circuit blocks, the output FIFO3
, input FIFO4, FIFO status register5. F
An IFO interrupt control circuit 6 is provided. Above output F
IF○3 sequentially stores the data transferred from the main CPU 15, and outputs the data onto the data bus 12 in the order in which it is stored in response to reading by the local CPU 2.

The above input FIF○4 sequentially stores data written by the local CPU 2 via the data bus 12, and stores data written by the local CPU 2 via the data bus 12.
The data stored in jlIN is output onto the data bus 16 in response to reading from the PU 15.

In addition, the FIF○ status register 5 is the output FIF
○3 and the amount of data stored in input FIFO4, for example,
It is constantly monitored and held using a monitor signal line 13 drawn out from a counter or the like inside O. FIFO status register 5 can be read by either the main or local CPU.

Internal bus 12 for reading from local CPU 2
In addition, for reading from the main CPU 15, information regarding the data amount of each input/output FIFO is output onto the external data bus 16.

Further, the status register 5 may have only a bit indicating whether the FIFO is empty or full, or may have a bit indicating whether the FIFO is empty or full.
The data amount may be shown in stages such as 4, or the amount of data may be shown in bytes.

On the other hand, the FIFO interrupt control circuit 6 issues an interrupt to the local CPU 2 using the interrupt request signal line 14 and to the main CPU 15 using the external interrupt request signal line 17 according to the contents of the FIFO status register 5. make a request.

Note that the I10 port 11 is connected to an external I10 device 18 and performs data transfer under the control of the local CPU 2. 5CIIO is a serial transfer interface for the local CPU 2. ROM8 stores a program that controls the operation of local CPU2. The RAM 7 is used as a work area when the local CPU 2 operates. Also.

The timer 9 is used to generate a timer interrupt signal to the local CPU 2 and to measure the cycle of external events.

In the system of the above embodiment, the main CPU 15 can transmit data to the output FIFO 3 until it becomes full, regardless of the operation of the local CPU 2.

Therefore, there is no need to wait for the local CPU 2 to finish the slow Ilo processing, and that time can be used for other processing, making it possible to improve the throughput of the entire system.

In addition, in the reception process, for example, the external I10 device 18
There is no need to receive data sent from the interrupt control circuit 6 each time, and the data accumulates in the input FIFO to a certain extent.
Since the main CPU 5 can process the interrupt request after receiving it, the main CPU 5 can receive data without interrupting the series of processes.

Further, since the output FIFO 3 and the input FIFO 4 are provided separately, it is possible to transmit data by the main CPU 15 and transmit data by the local CPU 2 at the same time.

In the above embodiment, the FIF○ status register 5
Assuming that the amount of data stored in FIFOs 3 and 4 is held in
In addition to the amount of transmitted and received data, the status register 5 is also provided with a beep 1 to indicate the end of data transfer, and when a series of data transfers is completed, this bit is set to I by some means.
By setting I II II, it is possible to cause the interrupt control circuit 6 to output an interrupt request signal before the FIFO becomes full, and to notify the transfer destination CPU that data has been transferred.

As explained above, the single-chip microcontroller of the above embodiment has two PIFs, 0 and 0 for data input/output.
A FIFO status register is provided to indicate the data storage status of the FO, and depending on the contents of the status register, an interrupt is used to notify the external or external and internal processors that data has been transferred.
When transferring data between two multiprocessors connected to each other, there is no need to first store the data in internal RAM, and the data can be transferred to the FIF without waiting for processing by the other processor.
The ability to continue sending data until O is full has the effect of increasing data transfer efficiency and improving system throughput I.

In addition, since the processor is automatically notified when the input/output FIFO becomes full, there is no need to constantly monitor whether or not there is data transfer. Now, if you try to increase the amount of data communication for - times, the effective address space will be narrowed down, but in the above example where FIFO is used for data transfer, regardless of the size of FIFO capacity, only one address can be used. Since all that is required is allocation, the effective address space becomes wider.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above-mentioned embodiment, the large FrF○ and the output FIFO are provided separately, but it is also possible to provide only one of them, or to provide a bidirectional FIFO.

In the above explanation, the invention made by the present inventor was mainly applied to a system using a single-chip microcomputer with a built-in FIFO as an I10 controller, which is the field of application in which the invention was made by the present inventor, but this invention is not limited to that. It can be widely used when used as a slave processor.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, by simply adding hardware, it is possible to increase the efficiency of data transfer between microprocessors in a multiprocessor system and improve the system throughput.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a single-chip microcomputer according to the present invention and an example of a multiprocessor system using the same as an I10 controller. 1... Single-chip microcomputer, 10... Serial communication interface circuit. 12...Internal bus, 13...Monitor signal line, 1
4.17... Interrupt signal line, 16... External data bus. 'L Figure 111'

Claims (1)

[Claims] 1. Data processing characterized by being connected to an external data bus and equipped with a first-in, first-out type data buffer that enables data transfer with other data processing devices. Device. 2. The data processing device according to claim 1, further comprising a control circuit that outputs a signal prompting the control means to transfer data when the data in the data buffer reaches a predetermined amount. . 3. The data processing device according to claim 1 or 2, further comprising a status register capable of displaying at least the data storage state in the data buffer.