JPH0287594A - Manufacture of hybrid integrated circuit device - Google Patents

Manufacture of hybrid integrated circuit device

Info

Publication number
JPH0287594A
JPH0287594A JP63239959A JP23995988A JPH0287594A JP H0287594 A JPH0287594 A JP H0287594A JP 63239959 A JP63239959 A JP 63239959A JP 23995988 A JP23995988 A JP 23995988A JP H0287594 A JPH0287594 A JP H0287594A
Authority
JP
Japan
Prior art keywords
solder
circuit board
lead
leads
clip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63239959A
Other languages
Japanese (ja)
Other versions
JPH0756911B2 (en
Inventor
Yasuo Ogawa
小川 康男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP63239959A priority Critical patent/JPH0756911B2/en
Publication of JPH0287594A publication Critical patent/JPH0287594A/en
Publication of JPH0756911B2 publication Critical patent/JPH0756911B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE:To enable externally connecting leads to be soldered to a circuit board efficiently by covering a horizontally extended part adjacent to a clip fitting section of the board with a covering jig formed of a material resistive to solder. CONSTITUTION:In order to solder externally connecting leads to a lead land provided on the periphery of a circuit board, a peripheral region (e) other than the clip fitting section of the board adjacent to clip fitting sections of the leads is covered with a covering jig (f) having a special construction and formed of a special material, namely a material having resistance to solder so that the region (e) is not brought into direct contact with molten solder. Further, heat of the molten solder is prevented from being transferred to soldering sections of components mounted on the board by effect of surface tension. The solder-resistive material unwettable by the solder may be a thermally stable resin such as epoxy glass fiber or bakelite. According to this method, the externally connecting leads can be soldered to the lead land of the circuit board efficiently without the risk of causing the electronic components packaged around the fitting section to fall down because these component are prevented from increase in temperature.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は混成集積回路装置の製造方法に関し、さらに詳
しくは混成集積回路基板への外部接続用リードの半田付
は法に特別の改善を含む同回路装置の製造方法に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a hybrid integrated circuit device, and more particularly to a method for manufacturing a hybrid integrated circuit device, and more particularly, the soldering of external connection leads to a hybrid integrated circuit board includes special improvements in the method. The present invention relates to a method of manufacturing the circuit device.

[従来の技術] 従来の混成集積回路装置の一般的製造方法を工程順に示
せば第6a〜6r図の如くであり下記の工程■〜■から
成っている。
[Prior Art] A conventional general manufacturing method for a hybrid integrated circuit device is shown in the order of steps as shown in FIGS. 6a to 6r, and consists of the following steps 1 to 2.

■ アルミナ基板1の一方または両方の主面にスクリー
ン印刷によりAg−Pd等の導体材料ペーストを塗布し
焼き付は処理して厚膜配線導体2および部品ランド3を
形成し、該アルミナ基板の少なくとも一方の縁辺部にそ
れぞれ前記厚膜配線導体に接続するように複数の外部接
続用リードのリードランド4を前記と同様に形成した後
、前記厚膜配線導体に接続するようにスクリーン印刷に
よりRu O2等の抵抗材料ペーストを塗布し焼き付は
処理して厚膜抵抗体5を形成する(第6a図)。
■ A conductor material paste such as Ag-Pd is applied by screen printing to one or both main surfaces of the alumina substrate 1, and baking is processed to form the thick film wiring conductor 2 and the component land 3, and at least After forming lead lands 4 for a plurality of external connection leads on one edge in the same manner as described above so as to connect to the thick film wiring conductor, RuO2 is formed by screen printing so as to connect to the thick film wiring conductor. The thick film resistor 5 is formed by applying a resistive material paste such as the above, and processing the baking process (FIG. 6a).

■ こうして得られた厚膜回路基板主面上の前記部品ラ
ンド3およびリードランド4を除外した部分にスクリー
ン印刷により保護ガラスを印刷し焼き付は処理して保護
ガラス層6を形成する(第6b図)。
■ A protective glass is printed by screen printing on the main surface of the thick film circuit board obtained in this manner, excluding the component lands 3 and lead lands 4, and the baking process is performed to form a protective glass layer 6 (Step 6b). figure).

■ 上記により得られた厚膜回路基板の前記部品ランド
3上に半田ペーストを印刷した後、チップ状電子部品7
,8.9等を搭載し、リフロー半田付は炉で熱処理して
部品ランドにこれらの電子部品を半田付け(S)により
導電固着する(第6cオ)。
■ After printing solder paste on the component land 3 of the thick film circuit board obtained above, the chip-shaped electronic component 7
, 8.9, etc., and heat-treated in a furnace for reflow soldering, and conductively fixed these electronic components to the component lands by soldering (S) (6th c).

■ 上記の電子部品を実装した厚膜回路基板上に形成し
たそれぞれの厚膜抵抗体5にレーザートリミング装置に
より切り溝10を形成して抵抗値の調整を行う(第6d
図)。
■ Cut grooves 10 are formed using a laser trimming device in each thick film resistor 5 formed on the thick film circuit board on which the above electronic components are mounted to adjust the resistance value (6th d
figure).

■ 上記により得られた混成集積回路基板上に設けられ
ている前記複数のリードランドにそれぞれ外部接続用リ
ード11のクリップ部11aを嵌合させる(第6c図)
■ Fit the clip portions 11a of the external connection leads 11 into the plurality of lead lands provided on the hybrid integrated circuit board obtained as described above (Fig. 6c).
.

■ これらのリード嵌合部が半田12中に没するように
回路基板を半田中に浸漬して、各リードランドに前記リ
ードのクリップ部11aを半田付けする(第6r図)。
(2) Dip the circuit board into solder so that these lead fitting parts are submerged in the solder 12, and solder the clip parts 11a of the leads to each lead land (Fig. 6r).

■ 上記により得られた混成集積回路基板を、前記外部
接続用リード11のリード部11bとタイバ一部lie
の部分を除いて、他の全部分をエポキシ樹脂あるいはフ
ェノール樹脂等の耐湿性を有する絶縁塗料にデイツプし
た後、熱処理により該絶縁性樹脂塗料を硬化させて保護
被膜を形成する。
■ The hybrid integrated circuit board obtained above is connected to the lead part 11b of the external connection lead 11 and a part of the tie bar.
Except for this part, all other parts are dipped in a moisture-resistant insulating paint such as epoxy resin or phenol resin, and then the insulating resin paint is cured by heat treatment to form a protective film.

■ 上記により保護被膜を形成した混成集積回路の一部
を成している複数の外部接続用リードから、それらを連
結しているタイバ一部lieを切り離して混成集積回路
装置を得る。
(2) A hybrid integrated circuit device is obtained by separating a portion of the tie bar connecting the plurality of external connection leads forming a part of the hybrid integrated circuit on which the protective film has been formed as described above.

し発明が解決しようとする課題] しかしながら、上記従来の製造方法により混成集積回路
装置をつくる場合には、第4a図および第4b図に示す
ように、混成集積回路基板Cの縁辺部に設けたリードラ
ンドにクリップリード(外部接続用リード)bを半田付
けする工程において、リードランドに嵌合させたクリッ
プリードの嵌合部が半田aの液面下に没するようにする
ため回路基板の縁辺部を半田中に半田液面よりある寸法
dだけ浸漬させる必要がある。このため回路基板縁辺部
はリードランドでない部分eも半11’Jの液面下に沈
められることになるので、このeの部分は当然電子部品
等を搭載できないデッドスペースとなる。そればかりで
なく、前記クリップ嵌合部の近くに電子部品が実装され
ている場合は、7Is子部品の半田付は部分か溶融半田
の液面に極めて接近することになるため、その半田付は
部分か再加熱され、その部分の半田が溶融して電子部品
が落下してしまうということが起こり得た。したがって
、従来の方法による場合は、第5図に示すように、たと
えば電子部品gの搭載はその半田付は部分が回路基板C
上のデッドスペースeの部分にかからないように搭載し
なければならないばかりてなく、電子部品の半田付は部
分はデッドスペースの境界線(すなわち半田の液面が回
路基板Cの面に接してつ(る線)hにあまり接近しない
ような位置に搭載しなければならなかった。
[Problems to be Solved by the Invention] However, when manufacturing a hybrid integrated circuit device using the above-mentioned conventional manufacturing method, as shown in FIGS. 4a and 4b, a In the process of soldering clip leads (external connection leads) b to lead lands, the edge of the circuit board is It is necessary to immerse the part into the solder by a certain distance d below the solder liquid level. Therefore, the portion e of the edge of the circuit board that is not a lead land is also submerged under the liquid level of the half 11'J, so naturally this portion e becomes a dead space in which electronic components and the like cannot be mounted. In addition, if electronic components are mounted near the clip fitting part, the soldering of the 7Is child components will be extremely close to the surface of the molten solder. It was possible that some parts would be reheated and the solder in those parts would melt, causing the electronic components to fall out. Therefore, when using the conventional method, as shown in FIG.
Not only must electronic components be mounted so that they do not touch the upper dead space e, but electronic components must be mounted so that they do not touch the dead space boundary (i.e., the solder level is in contact with the surface of the circuit board C). It had to be mounted in a position where it would not be too close to line (line) h.

何故なら、半田の熱で再加熱されてその部分の半田が溶
融して半田付けの一部または全部が部品ランドから離れ
てしまう恐れがあるからである。
This is because there is a risk that the solder will be reheated by the heat of the solder and the solder in that area will melt, causing part or all of the solder to separate from the component land.

したがって従来法による場合は、第5図に例示するよう
に、たとえば電子部品gを、デッドスペースの境界線り
からある程度離れた位置に搭載しなければならなかった
。すなわち、第5図にeで示すデッドスペースとなる部
分およびこれに極く近い部分には電子部品を実装するこ
とはできなかった。したがって、特に高密度実装を必要
とする場合などには、電子部品を実装した回路基板に作
業者が半田鏝を用いて前記複数の外部接続用リードをそ
れぞれ手作業により別の工程で半田付けしなければなら
ず、生産性が著しく低かった。
Therefore, in the case of the conventional method, as illustrated in FIG. 5, for example, the electronic component g had to be mounted at a certain distance from the boundary line of the dead space. That is, it was not possible to mount electronic components in the dead space shown by e in FIG. 5 and in the parts very close to this. Therefore, especially when high-density mounting is required, an operator may manually solder each of the plurality of external connection leads using a soldering iron to the circuit board on which electronic components are mounted in a separate process. productivity was extremely low.

本発明の目的は、上記従来の問題点を解決して、従来は
デッドスペースとならざるを得なかった部分にまで電子
部品を実装できるばかりでなく、リードランドの近傍や
半田の液面に近い部分に実装された電子部品を落下させ
ることなく、効率良く、外部接続用リードを回路基板に
半田付けすることが可能な混成集積回路装置の製造方法
を提供することにある。
The purpose of the present invention is to solve the above-mentioned conventional problems, and to not only make it possible to mount electronic components even in areas that conventionally had no choice but to be dead spaces, but also to make it possible to mount electronic components near lead lands and near the solder liquid surface. To provide a method for manufacturing a hybrid integrated circuit device, in which external connection leads can be efficiently soldered to a circuit board without dropping electronic components mounted on the parts.

[課題を解決するための手段] 回路基板の少なくとも一方の縁辺部に通常設けられるリ
ードランドに外部接続用リードを半田付けするに際し、
半田付は作業時において回路基板の外部接続用リードの
クリップ嵌合部に隣接する水平方向の延長部分となるク
リップ嵌合部でない縁辺部(すなわち第1図、第2図お
よび第3図等のeで示す部分)を、特殊の材質と構造を
持つカバー(被覆用治具)fで覆ってこの部分か直接溶
融半田に接触しないようにすると共に、表面張力の作用
による該カバーの使用効果によって溶融半田の熱が回路
基板上の搭載部品の半田付は部分に伝達されにくくなる
ように工夫し、これによって、前述の課題を解決するこ
とができた。上記eの部分は、従来の方法では、電子部
品を搭載できないデッドスペースとなっていたが、本発
明の方法に基づきカバーの形状および構造を工夫して実
装電子部品を保護すれば、このeの部分に電子部品が搭
載されていても流れ作業工程で外部接続用リードの半田
付けができるという利益も加わることになる。
[Means for solving the problem] When soldering an external connection lead to a lead land normally provided on at least one edge of a circuit board,
During soldering, soldering is carried out on the edges of the external connection leads of the circuit board adjacent to the clip-fitting parts, which are not the clip-fitting parts (i.e., as shown in Figures 1, 2, and 3). The part indicated by e) is covered with a cover (covering jig) f having a special material and structure to prevent this part from coming into direct contact with the molten solder, and the effect of using the cover due to the effect of surface tension The above-mentioned problem was solved by making it difficult for the heat of the molten solder to be transferred to the soldered parts of the components mounted on the circuit board. In the conventional method, the above part e is a dead space where electronic components cannot be mounted, but if the shape and structure of the cover are devised based on the method of the present invention to protect the mounted electronic components, this part e can be An added benefit is that even if electronic parts are mounted on the part, external connection leads can be soldered during the assembly process.

上に述べた本発明の方法は、次のように要約することが
できる。
The method of the invention described above can be summarized as follows.

回路基板の少なくとも一方の縁辺部に設けられているリ
ードランドに、外部接続用リードのクリップ部を嵌合さ
せた後、該クリップ嵌合部が充分に半田中に没する位置
まで回路基板を半田中に浸漬して前記リードの回路基板
への半田付けを行なう工程を含む混成集積回路装置の製
造方法において、半田付は作業時に回路基板の前記クリ
ップ嵌合部の隣接水平方向延長部分となるクリップ嵌合
部でない前記延長部分または少なくとも前記延長部分を
含むより広い部分を、少なくとも外周面が半田に濡れに
くい耐半田性の材料で構成されている断面が略コ字型の
被覆用治具で覆って回路基板の縁辺部を半田槽内に浸漬
することによって回路基板上に設けたリードランドに外
部接続用り−ドを半田付けすることを特徴とする混成集
積回路の製造方法。
After fitting the clip part of the external connection lead to the lead land provided on at least one edge of the circuit board, solder the circuit board to the position where the clip fitting part is fully submerged in the solder. In the method of manufacturing a hybrid integrated circuit device, the method includes the step of soldering the leads to a circuit board by immersing the leads into the circuit board, wherein the soldering is performed by immersing the leads into a clip that becomes an adjacent horizontal extension of the clip-fitting portion of the circuit board during operation. The extended portion that is not the mating portion or at least a wider portion including the extended portion is covered with a covering jig having a substantially U-shaped cross section and made of a solder-resistant material at least on the outer peripheral surface that is difficult to wet with solder. 1. A method of manufacturing a hybrid integrated circuit, which comprises soldering an external connection lead to a lead land provided on a circuit board by dipping the edge of the circuit board into a solder bath.

本発明の方法に使用する被覆用治具をつくるだめの半田
に濡れにくい耐半田性の材料としては、エポキシ−ガラ
スファイバー、ベークライト等の耐熱性樹脂などを用い
ることができる。また、アルミニウム、ステンレス等の
比較的半田に濡れに。
Epoxy-glass fibers, heat-resistant resins such as Bakelite, etc. can be used as solder-resistant materials that are difficult to get wet with solder for making the coating jig used in the method of the present invention. Also, aluminum, stainless steel, etc. are relatively resistant to solder.

くい金属を用いることや、金属の外周面に誘電体ガラス
ペーストを塗布し、焼き付は処理して半田レジスト層を
形成し、半田に濡れにくくすることもできる。
It is also possible to use a hard metal or to apply a dielectric glass paste to the outer peripheral surface of the metal and to treat baking to form a solder resist layer to make it difficult to get wet with solder.

被覆用治具として用いる断面が略コ字型の構造体として
は、回路基板の縁辺部に取り付は取りはずし容易に嵌合
可能な断面が略コ字型のものであれば何でもよいが、フ
ロー(噴流)半田槽に浸漬した際に半田のはじきを良く
するために、第7図(ロ)および(ハ)などに示すよう
に、半田の噴流を側面方向に導く鍔部を設けると、より
効果的である。
The structure with a substantially U-shaped cross section to be used as a coating jig may be any structure with a substantially U-shaped cross section that can be easily attached to and removed from the edge of the circuit board. (Jet flow) In order to improve the repellency of solder when immersed in a solder bath, it is recommended to provide a flange that guides the solder jet toward the side, as shown in Figures 7 (B) and (C). Effective.

本発明の実施に好都合に使用できる被覆用治具の幾つか
の例を第7図(イ)〜(ト)に示した。
Some examples of coating jigs that can be advantageously used in carrying out the present invention are shown in FIGS.

被覆用治具は回路基板の縁辺部に容易に取り付けること
ができ、しかも作業中安定に保持されているよう、弾性
材料でできていることが好ましい。
Preferably, the coating jig is made of a resilient material so that it can be easily attached to the edge of the circuit board and yet remains stable during operation.

この目的に好都合に使用できる弾性体としては、回路基
板の縁辺部に嵌合可能な弾性を有する耐半田性のもので
あれば何でもよいが、上に挙げた樹脂や金属を単独で使
用できるほか、回路基板と接触する部分にシリコーンゴ
ムを配して基板との密着性を向上させることも可能であ
り好ましい。
Any elastic body that can be conveniently used for this purpose may be any elastic body that is elastic enough to fit around the edge of the circuit board and is resistant to solder, but the resins and metals mentioned above can also be used alone. It is also possible and preferable to arrange silicone rubber on the portion that comes into contact with the circuit board to improve the adhesion to the board.

[作  用コ 本発明に従って混成集積回路基板縁辺部に設けたリード
ランドに外部接続用リードを半田付けする場合は、基板
縁辺部のリードランドでない部分を、少なくとも外表面
が半田に濡れにくい耐半田性の材料でつくった略コ字型
の被覆用治具で覆って半田付けを行なうので、従来はデ
ッドラインとなっていたこの被覆されている部分にも、
搭載電子部品またはその半田付は部分が存在していても
一向に差しつかえない。溶融半田との接触は起らす、半
田の熱も被覆用治具でさえぎられるので半日付は部分が
再溶融して部品が脱落するようなことは起らないからで
ある。治具の少なくとも外表面は半田に濡れにくい材料
でつくられているので、半田の表面張力によって半田が
治具の外表面からはじかれ、特に鍔部のある場合には、
半田の液面はたとえば第4a図に示すような形となり、
半田の持つ熱は基板上に搭載された電子部品に伝わりに
くくなるので好ましい。したがって、たとえば第4b図
に示すように、電子部品gの搭載可能の範囲が極めて縁
辺部に近い位置まで広がり、実装密度を高めることがで
きる。
[Function] When soldering external connection leads to lead lands provided on the edge of a hybrid integrated circuit board according to the present invention, the portions of the edge of the board that are not lead lands are soldered with at least the outer surface resistant to solder. Soldering is performed by covering the covered part with a roughly U-shaped covering jig made of a transparent material, so even this covered part, which conventionally had a deadline, can be soldered.
There is no problem with the mounted electronic components or their soldering even if some parts are present. Contact with molten solder occurs, but since the heat of the solder is blocked by the covering jig, parts of the half date do not re-melt and parts fall off. At least the outer surface of the jig is made of a material that is difficult to wet with solder, so the surface tension of the solder will cause the solder to be repelled from the outer surface of the jig, especially if there is a flange.
For example, the solder liquid level has a shape as shown in Figure 4a,
This is preferable because the heat of the solder is difficult to transfer to the electronic components mounted on the board. Therefore, as shown in FIG. 4b, for example, the range in which the electronic component g can be mounted is expanded to a position extremely close to the edge, and the mounting density can be increased.

実施例 ■ 第6a図に示すようなアルミナ基板1の表面にスク
リーン印刷によりAg−Pdペーストを塗布し、150
℃で10分間乾燥した後850℃で10分間焼き付は処
理して厚膜配線導体5、部品ランド3、およびリードラ
ンド4を形成し、さらに前記厚膜配線導体に接続するよ
うにスクリーン印刷によりRu O2系抵抗ペーストを
塗布し、150°Cで10分間乾燥した後850℃で1
0分間焼き付は処理して厚膜抵抗体5を形成した。
Example ■Ag-Pd paste was applied by screen printing on the surface of an alumina substrate 1 as shown in Fig. 6a.
℃ for 10 minutes, and then baked at 850℃ for 10 minutes to form thick film wiring conductors 5, component lands 3, and lead lands 4, and further connected to the thick film wiring conductors by screen printing. Apply RuO2-based resistance paste, dry at 150°C for 10 minutes, and then dry at 850°C for 1
A thick film resistor 5 was formed by baking for 0 minutes.

■ こうして得られた厚膜回路基板の表面の部品ランド
3およびリードランド4以外の部分にスクリーン印刷に
より保護ガラスを印刷し、150℃で10分間乾燥した
後530℃で2分間焼き付は処理して保護ガラス層6を
形成した。
■ Protective glass was printed on the surface of the thus obtained thick film circuit board other than component lands 3 and lead lands 4 by screen printing, dried at 150°C for 10 minutes, and then baked at 530°C for 2 minutes. A protective glass layer 6 was formed.

■ 上記で得られた厚膜回路基板の前記部品ランド3上
に半田ペーストを印刷した後、モールド型半導体7、チ
ップコンデンサ8、トランジスタ9などのチップ状電子
部品を搭載し、リフロー半田付は炉で230℃で熱処理
して前記部品ランド3に電子部品7,8.9などを半田
付けした。
■ After printing solder paste on the component land 3 of the thick film circuit board obtained above, chip-shaped electronic components such as the molded semiconductor 7, chip capacitor 8, and transistor 9 are mounted, and reflow soldering is carried out in a furnace. The electronic components 7, 8, 9, etc. were soldered to the component lands 3 by heat treatment at 230°C.

■ 上記電子部品を実装した厚膜回路基板の前記それぞ
れの厚膜抵抗体5について、レーザートリミング装置に
より抵抗値の調整を行った。
(2) The resistance value of each of the thick film resistors 5 of the thick film circuit board on which the electronic components were mounted was adjusted using a laser trimming device.

■ 上記で得られた混成集積回路基板上の複数のリード
ランド4にそれぞれ外部接続用リードのクリップ部を嵌
合させた。
(2) The clip portions of the external connection leads were respectively fitted into the plurality of lead lands 4 on the hybrid integrated circuit board obtained above.

■ 上記混成集積回路基板の外部接続用リードのクリッ
プ部が嵌合された縁辺部の前記リード嵌合部以外の部分
に、エポキシ−ガラスファイバーを断面か略コ字型に加
工してなる治具を嵌合させた状態で、前記回路基板の縁
辺部を235°Cのフロー(噴流)半田槽内に浸漬して
回路基板のリードランドに外部接続用リードを半田付け
した。
■ A jig made by processing epoxy glass fiber into a substantially U-shaped cross section on the edge portion of the hybrid integrated circuit board where the clip portion of the external connection lead is fitted, other than the lead fitting portion. In the fitted state, the edges of the circuit board were immersed in a flow (jet) solder tank at 235° C., and external connection leads were soldered to the lead lands of the circuit board.

■ 上記混成集積回路基板の縁辺部より、前記治具を取
り外した。
(2) The jig was removed from the edge of the hybrid integrated circuit board.

上記の半田付けにおいては、被覆用治具を使用しなけれ
ば半田への浸漬時に電子部品が半田液面と接する筈の位
置にも電子部品が搭載されていたが、電子部品の半田付
は部分の再溶融による離脱などの不都合は全く起らず、
外部接続用リードのリードランドへの接続は極めて良好
に行なうことができた。
In the soldering process described above, electronic components were mounted in positions where they would have come into contact with the solder liquid level when immersed in solder if a coating jig was not used. No inconveniences such as separation due to remelting occur,
The external connection lead could be connected to the lead land extremely well.

[発明の効果コ 本発明によれば、混成集積回路基板の縁辺部に外部接続
用リードのクリップ部を嵌合させ、該縁辺部を半田槽に
浸漬して前記リードを回路基板のリードランドに半田付
けする際に、前記リード嵌合部の周辺に実装された電子
部品の半田付は部分の温度上昇が防がれるので、実装部
品を落下させることなく外部接続用リードを効率よく半
田付けすることが可能となる。
[Effects of the Invention] According to the present invention, the clip portion of the external connection lead is fitted to the edge portion of the hybrid integrated circuit board, and the edge portion is immersed in a solder bath to attach the lead to the lead land of the circuit board. When soldering, electronic components mounted around the lead fitting portion are prevented from increasing in temperature, so external connection leads can be efficiently soldered without dropping the mounted components. becomes possible.

また、従来はデッドスペースとなっていた部分に電子部
品が搭載されていても、その部品を保護するための被覆
用治具を取り付けることによって、リードランドへの外
部接続用リードの半田付けを流れ作業で支障なく行なう
ことかできるので、作業効率を低下させることなく実装
密度を高めることができる。
In addition, even if electronic components are mounted in areas that were traditionally dead spaces, by attaching a covering jig to protect the components, soldering of external connection leads to lead lands can be made easier. Since the work can be carried out without any trouble, the packaging density can be increased without reducing work efficiency.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は、本発明に従って、混成集積回路
基、板縁辺部のリードランド以外の部分を被コ用治具で
覆って、前記縁辺部を半田中に浸漬I−で外部接続用リ
ードをリードランドに接続する場合の基板と半田との接
触の状態を示す概念図である。 第3図は回路基板の縁辺部に被覆用治具をつけて該縁辺
部を半田中に浸漬した状態を立体的に示す斜視図である
。 第4a図は電子部品を搭載した回路基板の一方の縁辺部
のリードランド以外の部分を鍔つきの治具で覆って回路
基板を半田中に浸漬した状態を示す側面図である。 第4b図は第4a図の場合についての正面図である。 第5図は従来の方法に従って、回路基板の縁辺部を治具
で覆うことなく基板を半田中に浸漬した状態を示す正面
図である。 第6a図〜第6r図は、典型的な従来の混成集積回路装
置の製造方法を工程順に示したものである。 第7図は本発明の実施に好都合に使用できる被覆用治具
の数例についての斜視図である。 図中の記号は次のものをそれぞれ表わす。 a・・・半 1)     b・・・クリップリードC
・・・回路基板     d・・・半田浸漬寸法e・・
・デッドスペース  f・・・被覆用治具g・・・電子
部品 h・・・デッドスペースの境界線 1・・・アルミナ基板   2・・・厚膜配線導体3・
・・部品ランド    4・・・リードランド5・・・
厚膜抵抗体    6・・・保護ガラス層7・・・モー
ルド型半導体 8・・・チップコンデンサ9・・・トラ
ンジスタ [0・・・レーザートリミングによる切り溝11・・・
外部接続用リード LLa・・・クリップ部Llb・・
・リード部    11c・・・タイバ一部12・・・
半田
FIGS. 1 and 2 show a hybrid integrated circuit board according to the present invention, in which the edge of the board other than the lead lands is covered with a jig, and the edge is immersed in solder for external connection. FIG. 4 is a conceptual diagram showing the state of contact between the board and solder when connecting the lead to the lead land. FIG. 3 is a three-dimensional perspective view showing a state in which a coating jig is attached to the edge of the circuit board and the edge is immersed in solder. FIG. 4a is a side view showing a state in which the circuit board on which electronic components are mounted is immersed in solder with the portions other than the lead lands on one edge of the circuit board covered with a jig with a flange. FIG. 4b is a front view of the case of FIG. 4a. FIG. 5 is a front view showing a circuit board immersed in solder without covering the edges of the circuit board with a jig according to the conventional method. FIGS. 6a to 6r show a typical conventional method for manufacturing a hybrid integrated circuit device in the order of steps. FIG. 7 is a perspective view of several examples of coating jigs that can be advantageously used in the practice of the present invention. The symbols in the figure represent the following, respectively. a...Half 1) b...Clip lead C
...Circuit board d...Solder immersion dimension e...
・Dead space f...Covering jig g...Electronic component h...Boundary line of dead space 1...Alumina substrate 2...Thick film wiring conductor 3.
...Parts land 4...Lead land 5...
Thick film resistor 6... Protective glass layer 7... Molded semiconductor 8... Chip capacitor 9... Transistor [0... Cut groove 11 by laser trimming...
External connection lead LLa...Clip part Llb...
・Lead part 11c...Tie bar part 12...
solder

Claims (1)

【特許請求の範囲】[Claims]  回路基板の少なくとも一方の縁辺部に形成されている
リードランドに、外部接続用リードのクリップ部を嵌合
させた後、該クリップ嵌合部が充分に半田中に没する位
置まで回路基板を半田中に浸漬して前記リードの回路基
板への半田付けを行なう工程を含む混成集積回路装置の
製造方法において、半田付け作業時に回路基板の前記ク
リップ嵌合部の隣接水平方向延長部分となるクリップ嵌
合部でない前記延長部分または少なくとも前記延長部分
を含むより広い部分を、少なくとも外周面が半田に濡れ
にくい耐半田性の材料で構成されている断面が略コ字型
の被覆用治具で覆って回路基板の縁辺部を半田槽内に浸
漬することによって回路基板上に設けたリードランドに
外部接続用リードを半田付けすることを特徴とする混成
集積回路装置の製造方法。
After fitting the clip part of the external connection lead to the lead land formed on at least one edge of the circuit board, solder the circuit board to the position where the clip fitting part is fully submerged in the solder. In the method of manufacturing a hybrid integrated circuit device, the method includes the step of soldering the leads to a circuit board by immersing the leads in the circuit board, the clip fitting being an adjacent horizontal extension of the clip fitting part of the circuit board during the soldering operation. Covering the extended portion that is not the joint, or at least a wider portion including the extended portion, with a covering jig having a substantially U-shaped cross section and having at least an outer peripheral surface made of a solder-resistant material that does not easily wet with solder. 1. A method of manufacturing a hybrid integrated circuit device, which comprises soldering external connection leads to lead lands provided on a circuit board by immersing an edge of the circuit board in a solder bath.
JP63239959A 1988-09-26 1988-09-26 Method for manufacturing hybrid integrated circuit device Expired - Lifetime JPH0756911B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63239959A JPH0756911B2 (en) 1988-09-26 1988-09-26 Method for manufacturing hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63239959A JPH0756911B2 (en) 1988-09-26 1988-09-26 Method for manufacturing hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPH0287594A true JPH0287594A (en) 1990-03-28
JPH0756911B2 JPH0756911B2 (en) 1995-06-14

Family

ID=17052377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63239959A Expired - Lifetime JPH0756911B2 (en) 1988-09-26 1988-09-26 Method for manufacturing hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0756911B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237323A (en) * 1990-11-21 1993-08-17 Hitachi, Ltd. Map retrieving system having a learning function

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6190293U (en) * 1984-11-20 1986-06-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6190293U (en) * 1984-11-20 1986-06-12

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237323A (en) * 1990-11-21 1993-08-17 Hitachi, Ltd. Map retrieving system having a learning function

Also Published As

Publication number Publication date
JPH0756911B2 (en) 1995-06-14

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