JPH0287632A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a junction area of a drain to a semiconductor substrate and to lower a drain capacitance by a method wherein a second groove reaching the semiconductor substrate is formed inside a first groove, an epitaxial layer is formed inside the groove and is flattened, a gate electrode is formed on its surface and the drain is formed in a region surrounded by an oxide film. CONSTITUTION:A second groove 4 reaching the surface of a silicon substrate 1 is formed inside a first groove 3. Then, an epitaxial growth operation is executed; the first and second grooves 3, 4 are filled; a P-type epitaxial layer 5 is grown up to the outside of the first groove 3. Then, the P-type epitaxial layer 5 protruding from the first groove 3 is shaved and flattened; after that, a gate oxide film 6 is grown on its surface. Then, a polycrystalline silicon film is formed on the whole surface; after that, it is patterned, and a gate electrode 7 is formed; after that, an oxide film is formed on its surface. During this process, the gate electrode 7 is formed so as to be spread over the first and second grooves in such a way that a channel region is connected to a silicon substrate 1. After that, a source 8 and a drain 9 are formed by making use of the gate electrode 7 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a source train for reducing drain capacitance.

[Conventional technology]

In the conventional MO3 structure semiconductor device, as shown in FIG. 3, the source 8 and drain 9 are formed by, for example, diffusion of N-type impurities, so that the junction capacitance between the silicon substrate 1 and the train 9 is smaller than that of the impurity diffusion layer. It has a structure that is attached to the bottom and sides.

In FIG. 3, 7 is a gate electrode, 10 is an interlayer film, and 1 is a gate electrode.
1 is a source electrode, 12 is a drain electrode, and 13 is a field oxide film.

[Problem to be solved by the invention]

In the above-mentioned conventional semiconductor device built in MOS 1'74, there is a large junction area between the drain and the silicon substrate, so a large drain capacitance is formed.
This has the disadvantage that the operating speed of the semiconductor device becomes slow.

An object of the present invention is to provide a method for manufacturing a semiconductor device with a fast reaction rate.

[Means to solve the problem]

The method of manufacturing a semiconductor device of the present invention includes the steps of: forming an oxide film on a semiconductor substrate, and then selectively etching the oxide film to make it thinner to form a first groove; A step of etching a portion of the oxide film to form a second trench reaching the semiconductor substrate, and a step of filling the first and second trenches and growing an epitaxial layer to the outside of the first trench, followed by selective etching. After removing the epitaxial layer outside the first groove by polishing to flatten the surface, and forming a gate oxide film on the flattened surface of the epitaxial layer, a gate electrode is formed on a predetermined portion of the gate oxide ridge. and a step of ion-implanting impurities using the gate electrode as a mask to form a source/drain in the epitaxial layer.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
A silicon oxide film 2 was formed to a thickness of 1 μm by thermal oxidation, and then buttered by anisotropic etching.
A first trench 3 with a depth of approximately 400 OA is formed.

Next, as shown in FIG. 1(b), a second groove 4 reaching the surface of the silicon substrate 1 is formed in a predetermined portion inside the first groove 3 by anisotropic etching.

Next, as shown in FIG. 1(c), S j, H2C,1
Epitaxial growth is performed using 2-HCl-H2 series gas and B2H6 as a dopant to fill the first and second trenches 3 and 4, and grow the P-type epitaxial layer 5 to the outside of the first trench 3.

Next, as shown in FIG. 1(d), the P-type epitaxial layer 5 protruding from the first groove 3 is polished and planarized by selective polishing, and then a gate oxide film 6 is formed on its surface by thermal oxidation. grow up.

Next, as shown in FIG. 1(e), a polycrystalline silicon film is formed on the entire surface and patterned to form a gate electrode 8! ! 7
After forming the gate electrode 7, a thickness of 20 mm is formed to protect the gate electrode 7.
A 0A oxide film is formed on the surface. At this time, the gate electrode 7 is formed to span the first and second trenches so that the channel region is connected to the silicon substrate 1. Thereafter, using the gate electrode 7 as a mask, As is implanted at a dose of 70 keV and a dose of 1.times.10@16 cm"" and activated by heat treatment to form a source 8 and a drain 9.

As shown in FIG. 1(f) below, the glabellar membrane 1 is
0 is formed by CVD method, contact holes are provided, and then A! Source electrode 11 and drain electrode 12 consisting of two films
is provided to complete the MOS type semiconductor device.

As described above, according to the first embodiment, the drain capacitance of the train 9 is reduced because one side surface and the bottom surface are in contact with the silicon oxide film 2.

FIGS. 2(a) to 2(e) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

First, as shown in FIG. 2(a), a silicon oxide film 2A with a thickness of 600A is formed on a P-type silicon substrate 1, and then phosphorus 21 is applied at a dose of 10A using a resist film 20 as a mask.
Ion implantation is performed under the condition of 13 cm-2.

Next, as shown in FIG. 2(b), after forming an N-type buried layer 22 by heat treatment, a silicon oxide film 2 having a thickness of 1)tm is formed by thermal oxidation. Next, as in the first embodiment, the first ? II3 and a second groove 4°4A are formed. Second
As the grooves, a groove 4A in contact with the N-type buried layer 22 and a groove 4 in contact with the silicon substrate 1 are formed.

Next, as shown in FIG. 2(C), the P-type epitaxial layer 1 (
After growing η5, the surface is planarized by scraping using a selective polysopping method.

Next, as shown in FIG. 2(d), phosphorus is ion-implanted into a region of the N-type buried M22 forming the P-channel MOS transistor, and the P-type epitaxial layer is changed to an N-type epitaxial layer 23. A gate oxide film 6 is formed on the surface.

Next, as shown in FIG. 2(e), an N-channel gate electrode 7A and a P-channel gate electrode 7B made of polycrystalline silicon are formed on the gate oxide film 6 by photolithography. Next, As ions are implanted into the N channel region side, and B (boron) is implanted into the P channel region side.
By ion-implanting to form sources 8A, 8B and drains 9A, 9B for each channel, an N-channel and P-channel MOS transistor in which each train 9A, 9B is in contact is completed.

By forming a common contact electrode for the trains 9A and 9B, an inverter made of C-MOS transistors can be formed.

In the second embodiment as well, since the area of each drain junction in contact with the silicon substrate is reduced, the drain capacitance is reduced and the speed of the transistor is increased.

〔Effect of the invention〕

As explained above, in the present invention, a first groove is formed in an oxide film on a semiconductor substrate, a second groove reaching the semiconductor substrate is formed in the first groove, and a second groove is formed in the first groove to reach the semiconductor substrate. An epitaxial layer is formed in the first trench, made flat by selective polishing, a gate electrode is formed on its surface via a gate oxide film, and then a drain is formed in the area surrounded by the oxide film by ion implantation. By forming this, the junction area between the train and the semiconductor substrate becomes smaller, and the drain capacitance is reduced, which has the effect of increasing the reaction speed of the semiconductor device.

1(a) to (f) and FIG. 2(a) to e) are cross-sectional views of semiconductor chips for explaining the first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view of a conventional semiconductor chip. 1 is a cross-sectional view of an example of a semiconductor device.

1...Silicon substrate, 2,2A...Silicon oxide film,
3...First groove, 4,4A...Second groove, 5...
P-type epitaxial layer, 6... gate oxide film, 7...
・Gate electrode, 7A...Gate electrode for N channel,
7B...P channel gate electrode, 8,8A8B.
...Source, 9.9A, 9B...Drain, 10...
Interlayer film, 11... Source electrode, 12... Drain electrode, 20... Resist film, 21... Phosphorus, 22...
- N type buried layer, 23... N type epitaxial layer.

Claims (1)

[Claims] a step of forming an oxide film on the semiconductor substrate and then selectively etching the oxide film to thin it to form a first groove; etching the oxide film in a predetermined portion within the first groove and etching the oxide film on the semiconductor substrate; forming a second groove reaching the first groove;
After filling the second trench and growing an epitaxial layer to the outside of the first trench, selective polishing is performed to grow the epitaxial layer to the outside of the first trench.
a step of removing the epitaxial layer outside the groove to planarize the surface; forming a gate oxide film on the planarized surface of the epitaxial layer; and then forming a gate electrode at a predetermined portion on the gate oxide film. A method for manufacturing a semiconductor device, comprising: a step of ion-implanting impurities using the gate electrode as a mask to form a source/drain in the epitaxial layer.