JPH0287721A - Analog input device - Google Patents

Abstract

PURPOSE:To correctly read and input an analog signal of plural channels by providing a device reading a channel number and a device reading an A/D conversion data of a relevant channel by the former reader. CONSTITUTION:An external analog input signal S1 is inputted to an adjustment circuit and sample-hold circuit multiplexer 3 samples and holds only an input data of a channel corresponding to the channel number sent from a timing generating circuit 5 from plural inputs. The output of the multiplexer 34 is subjected to A/D conversion 4 and a digital data S2 is obtained. When the A/D conversion of the A/D converter 4 is finished, an RDY signal S6 from the converter 4 is fed to a buffer 9. A channel number data S4 and a signal S6 are read via the buffer 9 and the data S2 is held in the buffer 10. When the signal S6 is the RDY, the digital data stored in the buffer 10 is read by using a digital data read instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an analog input device used in a control system using analog input.

(Prior Art) In conventional analog input devices, when inputting data from each channel, channel number data reading processing (
At the same time, read the RDY status of A/D conversion data) and R
Two processes are executed: DY to A/D conversion conversion data counting process.

An example of such a conventional analog input device will be explained with reference to the block diagram of FIG.

In FIG. 3, 1 is an analog input device, and this analog input device 1 is composed of an offset gain adjustment circuit 2, a multiplexer/sample hold circuit 3, an A/D converter 4, and a timing generation circuit 5. ing.

Note that 6 is a CPU board having a CPU 7.

Next, the operation of the conventional analog input device will be explained.

Analog input signal S1 from the outside is sent to A/D via adjustment circuit 2゜multiplexer/sample hold circuit 3.
It is input to converter 4. A from timing generation circuit 5
The conversion of the analog signal St is started by the /D conversion start signal S5, and the digital data S2 after A/D conversion, the analog input point number (channel number) data S4 and the A/D converter are sequentially sent from the timing generation circuit 5. Read the RDY signal S6 from 4. At this time, the digital data S2 after the A/I converter is valid (completely RDY).
If the signal S6 is output), the digital data S2 is immediately read and its value is stored without any pause.

The above operations are automatically repeated at regular intervals.

(Problem to be Solved by the Invention) In such a conventional analog input device 1, after reading the channel number data S4, the digital data S2 is read within a certain period of time (the time immediately before the data of the next channel is transmitted). If the A/D conversion data is not read, the A/D conversion data cannot be read correctly, making it impossible to insert a program, and furthermore, there are problems such as defective data being imported if there is a delay in data import.

The present invention was made to solve the above problems, and
The purpose is to provide an analog input device that allows insertion of programs (software) and also allows correct reading of A/D conversion data.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a plurality of channels for inputting analog signals.

The analog input device generates channel number data indicating the number of each of the plurality of channels in time series, selects only the analog input signal of the channel corresponding to the channel number data, and outputs the data value. The apparatus is characterized in that it comprises means for reading a channel number, means for holding A/D conversion data of the corresponding channel by the reading means, and means for reading the held data.

(Function) According to the analog input device of the present invention, since the A/D conversion data is latched at the same time as reading the channel number, the reliability of the hardware is improved. You can also insert programs. Furthermore, there is no need to introduce bad data.

(Example) An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, 8 is an analog input device, and this analog input device 8 includes an offset gain adjustment circuit 2, a multiplexer/sample hold circuit 3, an A/D converter 4, a timing generation circuit 5, and a buffer 9. , a latch buffer 10 and an invert gate 11.

By the way, the adjustment circuit 2 adjusts the offset and
This is for performing gain adjustment. Multiplexer
The sample and hold circuit 3 selects one designated by the channel number data S4 from among the plurality of input channels, and holds the input data of that channel. The A/D converter 4 converts analog input data from the multiplexer/sample hold circuit 3 into digital data S2, and the conversion is started by an A/D conversion start signal S5 from the timing generation circuit 5.

The timing generation circuit 5 generates channel number data S3.
S4 from the first channel number to the last channel number (
1 → 2 → 3) are transmitted sequentially at a constant cycle. The RDY signal s6 is a signal indicating completion of conversion from the A/D converter 3. This signal and channel number data S4 are input to the buffer 9, and the digital data S2 is input to the latch buffer 10.

The channel number read command S8 is input to the buffer 9 and further input to the latch buffer 10. This command reads the channel number data S4,
Furthermore, digital S2 is latched (held) at the trailing edge of the inverted command signal.

The digital data read command s7 reads the digital data s2 held above.

Next, the operation of this embodiment will be explained.

An analog input signal s1 from the outside of each channel is input to the adjustment circuit 2.

The analog input signal S1 of each channel output from the adjustment circuit 2 is input to the multiplexer/sample hold circuit 3, and only the input data of the channel corresponding to the channel number sent from the timing generation circuit 5 is allowed to pass through. -Holded in sample hold circuit 3. When the A/D conversion start signal S5, which is repeatedly generated at regular intervals from the timing generation circuit, is sent to the A/D converter 4, A/D conversion of the held analog data is started. Upon completion, the RDY signal S6 from the A/D converter 4 becomes valid. At this time, the digital data S2 output from the A/D converter 4 also becomes valid.

The timing generation circuit 5 automatically and repeatedly sends out channel number data S4 from number 1 to the last number data.

The CPU 7 (software) inputs a channel number read command S8, reads the channel number data S4 and the signal s6 via the buffer 9, and holds the digital data S2 in the buffer 10 at the trailing edge of this command. At this time, if the signal S6 is BUSY, the data is invalidated, and if it is RDY, then the digital data held in the latch buffer 10 is read by the digital data read command S7.6 Figure 2 is a timing diagram of the main signals of this embodiment. and the AID conversion start signal S5. R.D.Y.
Signal S6, channel number data S4. This figure shows the digital data S2 and the digital data readable area (this embodiment, the conventional example).

As described above, according to this embodiment, the area in which digital data can be read is larger than that of the conventional example, so that other processing can be performed before reading the digital data.

〔Effect of the invention〕

As described above, according to the present invention, digital data is held at the same time as channel number reading, so hardware reliability is improved.

Furthermore, since it takes time to read the digital data,
During this time, other software processing can be added, and even if the processing time overlaps with the time when the next channel data is transmitted, the data can be read correctly.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a timing diagram of the main signals shown in FIG. 1, and FIG. 3 is a block diagram of a conventional anlog input device. 1.8...Analog input device 2...Adjustment circuit 3
...Multiplexer/sample hold circuit 4...
A/D converter 5... Timing generation circuit 6... CPtJ board 7... CPU9.
...Buffer 10...Buffer with latch 11...Invert gate Fig. 1 (8733) Agent Patent attorney Yoshiaki Inomata (and 1 other person) Fig. 2

Claims (1)

[Claims] (1) Provides multiple channels for inputting analog signals, generates channel number data indicating the number of each of these multiple channels in chronological order, and only generates analog input signals of channels corresponding to the channel number data. In an analog input device for selecting a channel number and outputting the data value thereof, means for reading the channel number;
An analog input device comprising: means for holding A/D converted data of a corresponding channel by the reading means; and means for reading the held data.