JPH0288112U - - Google Patents
Info
- Publication number
- JPH0288112U JPH0288112U JP16637588U JP16637588U JPH0288112U JP H0288112 U JPH0288112 U JP H0288112U JP 16637588 U JP16637588 U JP 16637588U JP 16637588 U JP16637588 U JP 16637588U JP H0288112 U JPH0288112 U JP H0288112U
- Authority
- JP
- Japan
- Prior art keywords
- output
- calculation means
- synchronous rectifier
- circuit
- phase signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 8
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Transmission And Conversion Of Sensor Element Output (AREA)
Description
第１図はこの考案の実施例を示すブロツク図、
第２図は他の実施例を示すブロツク図である。
Figure 1 is a block diagram showing an embodiment of this invention.
FIG. 2 is a block diagram showing another embodiment.
Claims (1)
れぞれ同期整流する第１、第２、第３同期整流器
と、 その第２同期整流器の出力に対し１／２を乗算
する第１演算手段と、 上記第２同期整流器の出力に対し√３／２を乗
算する第２演算手段と、 上記第３同期整流器の出力に対し１／２を乗算
する第３演算手段と、 上記第３同期整流器の出力に対し√３／２を乗
算する第４演算手段と、 上記第１同期整流器の出力と、上記第１演算手
段の出力及び上記第３演算手段の出力との差をと
る第５演算手段と、 上記第４演算手段の出力と上記第２演算手段の
出力との差をとる第６演算手段と、 を具備するセルシン信号変換器。 (2) センシンの第２相信号に１／２を乗算する
第１乗算回路と、 上記セルシンの第２相信号に√３／２を乗算す
る第２乗算回路と、 上記セルシンの第３相信号に１／２を乗算する
第３乗算回路と、 上記セルシンの第３相信号に√３／２を乗算す
る第４乗算回路と、 上記セルシンの第１相信号と上記第１乗算回路
の出力及び上記第３乗算回路の出力との差をとる
第１減算回路と、 上記第２乗算回路の出力と上記第４乗算回路の
出力との差をとる第２減算回路と、 上記第１減算回路の出力を同期整流する第１同
期整流器と、 上記第２減算回路の出力を同期整流する第２同
期整流器と、 を具備するセルシン信号変換器。[Claims for Utility Model Registration] (1) First, second, and third synchronous rectifiers that synchronously rectify the first, second, and third phase signals of Selsyn, respectively, and the output of the second synchronous rectifier. a first arithmetic means for multiplying the output of the second synchronous rectifier by √3/2; a second arithmetic means for multiplying the output of the third synchronous rectifier by 1/2; 3 calculation means, 4th calculation means for multiplying the output of the third synchronous rectifier by √3/2, the output of the first synchronous rectifier, the output of the first calculation means and the third calculation means. A cell signal converter comprising: fifth calculation means for calculating the difference between the output of the fourth calculation means and the output of the second calculation means; and sixth calculation means for calculating the difference between the output of the fourth calculation means and the output of the second calculation means. (2) a first multiplier circuit that multiplies the second phase signal of the sensin by 1/2; a second multiplier circuit that multiplies the second phase signal of the sensin by √3/2; and a third phase signal of the sensin. a third multiplier circuit that multiplies the third phase signal of the Sersin by 1/2; a fourth multiplier circuit that multiplies the third phase signal of the Sersin by √3/2; a first phase signal of the Sersin and the output of the first multiplier circuit; a first subtraction circuit that takes the difference between the output of the third multiplication circuit; a second subtraction circuit that takes the difference between the output of the second multiplication circuit and the fourth multiplication circuit; A first synchronous rectifier that synchronously rectifies an output; and a second synchronous rectifier that synchronously rectifies an output of the second subtraction circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16637588U JPH0288112U (en) | 1988-12-22 | 1988-12-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16637588U JPH0288112U (en) | 1988-12-22 | 1988-12-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0288112U true JPH0288112U (en) | 1990-07-12 |
Family
ID=31453697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16637588U Pending JPH0288112U (en) | 1988-12-22 | 1988-12-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0288112U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5340341A (en) * | 1976-09-25 | 1978-04-12 | Mitsuo Matsumoto | Shooting game device |
| JPS58165310A (en) * | 1982-03-26 | 1983-09-30 | Fuji Electric Co Ltd | 3-phase/2-phase voltage converter |
-
1988
- 1988-12-22 JP JP16637588U patent/JPH0288112U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5340341A (en) * | 1976-09-25 | 1978-04-12 | Mitsuo Matsumoto | Shooting game device |
| JPS58165310A (en) * | 1982-03-26 | 1983-09-30 | Fuji Electric Co Ltd | 3-phase/2-phase voltage converter |
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