JPH0288977A - Method for testing semiconductor device - Google Patents

Method for testing semiconductor device

Info

Publication number
JPH0288977A
JPH0288977A JP24135988A JP24135988A JPH0288977A JP H0288977 A JPH0288977 A JP H0288977A JP 24135988 A JP24135988 A JP 24135988A JP 24135988 A JP24135988 A JP 24135988A JP H0288977 A JPH0288977 A JP H0288977A
Authority
JP
Japan
Prior art keywords
semiconductor device
plural
terminal
output voltage
current sources
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24135988A
Other languages
Japanese (ja)
Inventor
Teruo Shintani
新谷 輝雄
Kenji Yamada
健二 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP24135988A priority Critical patent/JPH0288977A/en
Publication of JPH0288977A publication Critical patent/JPH0288977A/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To instantaneously discriminate the propriety of a semiconductor device by inspecting the internal disconnection of the semiconductor device by simultaneously supplying electric currents from plural current sources to plural terminals of the semiconductor device and simultaneously reading the voltages across each terminal. CONSTITUTION:Electric currents from plural current sources 2 which are driven by a power source 1 are simultaneously supplied to plural terminal 4a-4n of a semiconductor device 4 to be tested through simultaneously opening and closing plural switches 3. In addition, the electric currents from the current sources 2 are supplied to an amplifier 6 through plural diodes 5 and fetched as an output voltage V0. When no internal disconnection exists in the device 4, the potential at each terminal 4a-4n is low and the output voltage V0 of the amplifier 6 is low, but, when internal disconnection exists, the voltage across the terminal connected with the disconnected part becomes extremely high and the output voltage V0 also becomes higher. Therefore, when the pointer of the measuring instrument scales out, the internal disconnection can be discriminated.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の断線を効率よ(測定する半導体装
置の試験方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a semiconductor device testing method for efficiently measuring disconnection in a semiconductor device.

従来の技術 一般に半導体装置の内部の断線試験を行うには、第2図
に示すように、電源1により駆動される電流源2からの
電流を被試験半導体装置(以下DUTと呼ぶ)4の隣接
端子4 a * 4 b間にスイッチ3を介して流し、
これらの端子間で発生する電圧を電圧計7で測定してい
た。
2. Description of the Related Art Generally, in order to conduct a disconnection test inside a semiconductor device, as shown in FIG. Flow through switch 3 between terminals 4a * 4b,
The voltage generated between these terminals was measured with a voltmeter 7.

このようにすれば、内部に断線が生じていないときは電
圧計7の電圧値が低し、断線が生じているときは高くな
るため、電圧計7の表示により内部の断線を測定するこ
とができる。
In this way, the voltage value on the voltmeter 7 will be low when there is no internal disconnection, and will be high when there is a disconnection, so it is possible to measure the internal disconnection based on the display on the voltmeter 7. can.

発明が解決しようとする課題 しかしながら、このような従来の方法では、DUT4が
大規模になり、端子数が多くなった場合、隣接する端子
を順次自動的に切換えて全端子を測定しなければならな
いため、試験項目が多くなり、試験時間も長くなり、検
査コストが高(なる。
Problems to be Solved by the Invention However, with such conventional methods, when the DUT 4 becomes large-scale and has a large number of terminals, it is necessary to automatically switch adjacent terminals one after another and measure all terminals. Therefore, the number of test items increases, the test time becomes longer, and the inspection cost becomes higher.

本発明はこのような従来の問題点を解決する半導体装置
の試験方法を提供するものである。
The present invention provides a method for testing semiconductor devices that solves these conventional problems.

課題を解決するための手段 本発明はDUTの接地端子を基準電位点に接続し、電流
源からの電流をDUTの複数の端子に同時に供給し、上
記複数の端子に発生する電圧を同時に読みとることによ
りDUT内の断線を測定するものである。
Means for Solving the Problems The present invention connects the ground terminal of the DUT to a reference potential point, simultaneously supplies current from a current source to multiple terminals of the DUT, and simultaneously reads the voltages generated at the multiple terminals. This is used to measure wire breakage within the DUT.

作用 このようにすれば、DUTの内部が断線していると、断
線箇所につながっている端子の電圧が高くなるから、こ
の電圧の変化を測定することによってDUTの不良判定
が瞬時に行える。
By doing this, if there is a disconnection inside the DUT, the voltage at the terminal connected to the disconnection point will increase, so by measuring the change in voltage, it is possible to instantly determine whether the DUT is defective.

実施例 以下、本発明の一実施例を第1図とともに説明する。Example An embodiment of the present invention will be described below with reference to FIG.

第1図において、電源1により駆動される複数の電流源
2からの電流が、同時に開閉する複数のスイッチ3を介
してDUT4の複数の端子4a〜4nに同時に供給され
る。また各電流源2からの電流は複数のダイオード5を
介して増幅器6に加えられ、出力電圧Voとしてとり出
される。DUTの接地端子4mは基準電位点(この例で
はアース)に接続されている。
In FIG. 1, currents from a plurality of current sources 2 driven by a power source 1 are simultaneously supplied to a plurality of terminals 4a to 4n of a DUT 4 via a plurality of switches 3 that open and close simultaneously. Further, the current from each current source 2 is applied to an amplifier 6 via a plurality of diodes 5, and taken out as an output voltage Vo. The ground terminal 4m of the DUT is connected to a reference potential point (ground in this example).

次に動作を説明する。Next, the operation will be explained.

DUT4に内部断線がないときは、各電流源2からの電
流は内部配線を通って接地端子4mへ達し、アースへと
流れる。このとき各端子48〜4nには所定の電位が発
生するが、その電圧値は小さい。したがって増幅器6の
出力電圧Voも小さい。
When there is no internal disconnection in the DUT 4, the current from each current source 2 passes through the internal wiring, reaches the ground terminal 4m, and flows to the ground. At this time, a predetermined potential is generated at each terminal 48 to 4n, but the voltage value is small. Therefore, the output voltage Vo of the amplifier 6 is also small.

ところが、内部に断線があると、断!sM所につながっ
た端子の電圧が極端に大きくなる。その結果出力電圧V
Oも大きくなる。したがって増幅器6の出力電圧Voを
測定器(図示せず)に接続すれば、測定器の針が振り切
れることによって内部断線があることがわかる。又、電
圧比較器等で自動的に良否を判定することもできる。
However, if there is a break inside, it will break! The voltage at the terminal connected to sM becomes extremely large. As a result, the output voltage V
O also becomes larger. Therefore, if the output voltage Vo of the amplifier 6 is connected to a measuring device (not shown), it can be seen that there is an internal disconnection when the needle of the measuring device swings out. Furthermore, it is also possible to automatically determine whether the product is good or bad using a voltage comparator or the like.

発明の効果 本発明はDUTの複数の端子に電流源がらの電流を同時
に加え、そのときの各端子の電圧を同時に読みとること
によってDUTの内部断線を検査するものであるから、
多数の端子を有するDUTであっても、−瞬のうちに良
否判定ができ、試験時間を大幅に短縮することができる
Effects of the Invention The present invention tests for internal disconnections in the DUT by simultaneously applying current from a current source to multiple terminals of the DUT and reading the voltage at each terminal at the same time.
Even for a DUT having a large number of terminals, pass/fail judgment can be made in an instant, and testing time can be significantly shortened.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における半導体装置の試験方
法を示す回路図、第2図は従来の半導体装置の試験方法
を示す回路図である。 l・・・・・・電源、2・・・・・・電流源、3・・・
・・・スイッチ、4・・・・・・被試験半導体装置、4
a〜4n・・・・・・端子、4m・・・・・・接地端子
、5・・・・・・ダイオード、6・・・・・・増幅器。 代理人の氏名 弁理士 粟野重孝 ばか1名1−・−電
 瀞 ? −・ t 流 渾 3−・・  ス  イ  リ  チ 4・−’If濁定竿jL#浅直 第 図 7−電圧計
FIG. 1 is a circuit diagram showing a method for testing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional method for testing a semiconductor device. l...Power supply, 2...Current source, 3...
...Switch, 4...Semiconductor device under test, 4
a to 4n...terminal, 4m...ground terminal, 5...diode, 6...amplifier. Agent's name: Patent attorney Shigetaka Awano Idiot 1 person 1--Den Toro? -・t Current flow 3-...Sui Rich 4・-'If turbidity setting rod jL# Shallow straight Figure 7-Voltmeter

Claims (1)

【特許請求の範囲】[Claims] 被試験半導体装置の接地端子を基準電位点に接続し、電
流源からの電流を上記被試験半導体装置の複数の端子に
同時に供給し、上記複数の端子に発生する電圧を同時に
読みとることにより上記被試験半導体装置内の断線を測
定することを特徴とする半導体装置の試験方法。
The ground terminal of the semiconductor device under test is connected to a reference potential point, current from a current source is simultaneously supplied to multiple terminals of the semiconductor device under test, and the voltages generated at the multiple terminals are simultaneously read. A method for testing a semiconductor device, characterized by measuring a disconnection in the semiconductor device under test.
JP24135988A 1988-09-27 1988-09-27 Method for testing semiconductor device Pending JPH0288977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24135988A JPH0288977A (en) 1988-09-27 1988-09-27 Method for testing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24135988A JPH0288977A (en) 1988-09-27 1988-09-27 Method for testing semiconductor device

Publications (1)

Publication Number Publication Date
JPH0288977A true JPH0288977A (en) 1990-03-29

Family

ID=17073120

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24135988A Pending JPH0288977A (en) 1988-09-27 1988-09-27 Method for testing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0288977A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100660856B1 (en) * 2005-01-26 2006-12-26 삼성전자주식회사 Multiple Voltage Monitoring Device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100660856B1 (en) * 2005-01-26 2006-12-26 삼성전자주식회사 Multiple Voltage Monitoring Device

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