JPH0289852U - - Google Patents
Info
- Publication number
- JPH0289852U JPH0289852U JP1988169745U JP16974588U JPH0289852U JP H0289852 U JPH0289852 U JP H0289852U JP 1988169745 U JP1988169745 U JP 1988169745U JP 16974588 U JP16974588 U JP 16974588U JP H0289852 U JPH0289852 U JP H0289852U
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- external lead
- conductive pattern
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図および第３図は本考案の実施例を示す断
面図、第２図はフレキシブル配線基板の断面図、
第４図は本考案の前提となる混成集積回路装置の
断面図である。 １′……外部リード、２……配線基板、４……
半導体ペレツト、９……フレキシブル配線基板。
面図、第２図はフレキシブル配線基板の断面図、
第４図は本考案の前提となる混成集積回路装置の
断面図である。 １′……外部リード、２……配線基板、４……
半導体ペレツト、９……フレキシブル配線基板。
Claims (1)
- 配線基板上にマウントした半導体ペレツト、配
線基板上の導電パターン、外部リード間をそれぞ
れ電気的に接続したものにおいて、上記導電パタ
ーンと外部リード間をフレキシブル配線基板にて
接続したことを特徴とする混成集積回路装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988169745U JPH0289852U (ja) | 1988-12-27 | 1988-12-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988169745U JPH0289852U (ja) | 1988-12-27 | 1988-12-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0289852U true JPH0289852U (ja) | 1990-07-17 |
Family
ID=31460078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988169745U Pending JPH0289852U (ja) | 1988-12-27 | 1988-12-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0289852U (ja) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009506553A (ja) | 2005-08-31 | 2009-02-12 | マイクロン テクノロジー， インク． | マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法 |
| US9299684B2 (en) | 2005-08-26 | 2016-03-29 | Micron Technology, Inc. | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
| JP2025102927A (ja) * | 2021-11-17 | 2025-07-08 | 株式会社デンソー | 半導体モジュール |
-
1988
- 1988-12-27 JP JP1988169745U patent/JPH0289852U/ja active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9299684B2 (en) | 2005-08-26 | 2016-03-29 | Micron Technology, Inc. | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
| US9583476B2 (en) | 2005-08-26 | 2017-02-28 | Micron Technology, Inc. | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
| US10153254B2 (en) | 2005-08-26 | 2018-12-11 | Micron Technology, Inc. | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
| US10861824B2 (en) | 2005-08-26 | 2020-12-08 | Micron Technology, Inc. | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
| JP2009506553A (ja) | 2005-08-31 | 2009-02-12 | マイクロン テクノロジー， インク． | マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法 |
| JP2025102927A (ja) * | 2021-11-17 | 2025-07-08 | 株式会社デンソー | 半導体モジュール |