JPH0290318A - Barrel shifter circuit - Google Patents

Abstract

PURPOSE:To realize a 1-chip structure with a high degree of integration for the p and n channel transistor TR groups of the transfer gates forming a barrel shifter circuit by separating these TRs from each other and arranging them into a matrix. CONSTITUTION:A barrel shifter circuit consists of transfer gates. A transfer gate includes the TR arrays 14 and 13 of p and n channel TR groups. The p and n channel TR 12 and 11 are arranged into a matrix for the arrays 14 and 13 separated from each other, and a boundary area which separates the TRs of different channels types from each other can be minimized. Thus the area occupied by a CMOS semiconductor integrated circuit is reduced and a 1-chip structure of TRs is obtained with a high degree of integration. Then the power consumption is decreased and the economical properties can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a barrel shifter circuit implemented as a CMOS circuit in a semiconductor integrated circuit.

[Conventional technology]

Conventionally, this type of barrel shifter circuit has been constructed using a TTL standard logic IC1 or a TTL gate array. FIG. 3 is a conceptual diagram of the operation of a conventional barrel shifter circuit. This barrel shifter circuit is a circuit that shifts data on N data buses by an arbitrary shift amount.

[Problem to be solved by the invention]

The conventional barrel shifter circuit described above requires the use of a large number of TTL standard logic ICs or a highly integrated and expensive gate array in order to cope with the increased number of bits of the data bus to improve the performance of electronic computers. This has the drawback of increasing system cost due to increased mounting area and power consumption. Therefore, there has been a demand for a barrel shifter circuit using a CMO3 type semiconductor integrated circuit, which has particularly low power consumption among semiconductor integrated circuits that have a proven track record in high-density integration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a barrel shifter circuit that solves these problems, has a reduced mounting area, reduces power consumption, and can be constructed at low cost.

[Means to solve the problem]

The configuration of the present invention is that in a barrel shifter circuit configured by a plurality of transfer gates on a CMO3 structure semiconductor integrated circuit, a P-channel transistor group and an N-channel transistor group constituting the transfer gate are arranged in a matrix. In addition, the present invention is characterized in that these two transistor groups are separately arranged.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In the figure, 11 is an N-channel transistor (no circle mark on the gate), 12 is a P-channel transistor (there is a circle mark on the gate), 1 to 4 (IN) are data input lines, and 5 to 8 (
OUT) is a data output line, and 20 to 23 (shift) are shift amount selection input lines. In the circuit of this embodiment, all transistor arrays 13 surrounded by dotted lines are of N-channel type, and all of the other transistor arrays 4 surrounded by dotted lines are of P-channel type. Since the boundary area for separating these P-channel type and N-channel type transistors 11 and 12 can be minimized, a high degree of integration is possible in the CMO3 type semiconductor integrated circuit.

Note that although this embodiment shows a case where there are four input and output data lines each, the number can be any number as long as it is two or more.

FIG. 2 is a circuit diagram of a second embodiment of the invention. This embodiment is an example in which an inverter circuit 16 for amplifying the output signal of the first embodiment is incorporated. In this embodiment, since the inverter circuit] 6 drives the data output lines 5 to 8, fan-out (FAN 0UT) design is facilitated, and the transistor group constituting the inverter circuit 16 is also separated like the transfer gate. This has the advantage that the boundary area is smaller than designing the barrel shifter circuit and the output amplifier circuit separately, and a higher degree of integration can be obtained.

〔Effect of the invention〕

As explained above, the present invention has the advantage that by implementing a CMOS circuit, it is possible to achieve high integration into a single chip, and at the same time, it is possible to reduce power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a barrel shifter which is an embodiment of the present invention.
FIG. 2 is a circuit diagram of a barrel shifter with an inverter output circuit according to a second embodiment of the present invention, and FIG. 3 is a conceptual diagram of the operation of a conventional barrel shifter circuit. 1 to 4...Input signal line (IN), 5 to 8...Output signal m (OUT), 11...N channel transistor, 12...P channel transistor, 13...N
Channel transistor, 14... P channel transistor, 15... Control signal inverter circuit, 16...
Inverter circuit for output signal amplification, 20-23...Shift amount selection input line.

Claims (1)

[Claims] In a barrel shifter circuit constituted by a plurality of transfer gates on a semiconductor integrated circuit having a CMOS structure, a P-channel transistor group and an N-channel transistor group constituting the transfer gate are respectively arranged in a matrix, and these two A barrel shifter circuit characterized by separately arranging transistor groups.