JPH0290334A - Simulation method for fault detection circuit - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a diagnostic method for an information processing device, and particularly to a logic simulation method suitable for checking the operation of a fault detection circuit for faults that occur during operation.

[Conventional technology]

Information processing devices such as large-scale computers are generally required to have a high degree of reliability due to their versatility, public nature, and real-time nature. To cope with this, failure detection circuits, automatic recovery mechanisms, and maintenance functions are pre-installed as part of information processing devices. At the same time that the fault detection circuit detects a fault that occurred during the operation of the information processing device, a defective replacement unit (package) containing the fault that caused the fault is sent.
The role of equipment diagnosis is to quickly recover from a faulty state by pointing out the problem and replacing it.

Detection rate is an index expressing the performance of device diagnosis.

Resolution is conventionally used. Detection rate is an index indicating the ability to detect a failure occurring within the device, and resolution is an index indicating the ability to narrow down the location of the defective replacement part that caused the failure when the failure is detected. The value of these detection rate 2 resolutions is determined by how the fault detection circuit is incorporated and arranged in the device. In order to achieve high-performance equipment diagnosis, it is important to design a fault detection circuit with high detection rate 2 resolution;

It is essential to accurately evaluate resolution at the logic design stage.

Conventionally, the H1 calculation for a detection rate of 9 resolution has been performed based on information obtained by manually tracing the logic diagram of the entire device. In recent years, with the increase in the scale of equipment due to the high integration of parts, a sharp increase in the number of man-hours and a decline in reliability due to manual errors have become evident, and automation has been desperately needed.

From this background, the detection rate of fault detection circuits.

ELT (Error Latch Tra
ce) method is published in Proceedings of the Design Automation Conference (1981), pp. 355-359 (DAC (1981), pp. 355-3).
59). With this ELT method, the performance of the fault detection circuit can be easily grasped at the design stage, and design changes can be made to improve performance as necessary.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not consider automating the operation check of the fault detection circuit, and does not take into account the automatic check of the operation of the fault detection circuit as the logical scale of the device increases (that is, the number of fault detection circuits increases). Problems remained such as an increase in the amount of manpower required and a decrease in reliability due to errors in manual work (such as associating fault detection circuits with the logic to be checked).

Furthermore, in the above conventional technology, performance evaluation (calculation of detection rate 2 resolution) is performed on the premise that 100% of faults that occur within the coverage area of the fault detection circuit can be detected by the fault detection circuit. If the failure detection circuit is inoperable, its evaluation is useless, so checking the operation is important.

The purpose of the present invention is to solve such conventional problems, to automatically check the operation of a highly accurate fault detection circuit based on the logic design information of an information processing device, and to prevent faults caused by an increase in the logical scale of the device. It is an object of the present invention to provide a simulation method for a fault detection circuit that makes it possible to reduce the number of manual steps involved in checking the operation of the detection circuit.

[Means to solve the problem]

In order to achieve the above object, the fault detection circuit simulation method of the present invention provides a logic In a logic simulation method that uses verification data that causes the fault detection circuit to detect a fault (turns on) at the design stage to confirm whether or not the fault detection circuit operates normally, the logic design information of the information processing device is input. , means for automatically extracting a detectable area (defense range) of a fault detection circuit including a circuit for detecting a fault and a circuit group (register group) to be detected by the fault detection circuit from the logical design information; means for automatically creating verification data for confirming the operation of a fault detection circuit; and applying the verification data to a specific part within the coverage area of the fault detection circuit to perform a logic simulation; It is characterized by having means for checking whether or not it operates normally.

[Effect]

Typical examples of fault detection circuits include parity generators (PG) and parity checkers (PC), which are widely used in information processing devices. FIG. 3 shows a typical usage example of a parity generator and parity checker. A parity checker (PC) 350 can detect a 1-bit error occurring in the data transfer path 330 between the input side register 310 and the output side register 340. The input side register 310 is used as a parity generation target register (PGR), and the output side register 340 is used as a parity check target register (PGR).
CR). When a failure occurs in the data transfer path 330 and the parity checker (PC) 350 detects the failure, the failure detection indicator latch (CHK) 360 lights up.
This allows the system to detect the occurrence of a failure.

The data transfer path surrounded by the parity generation target register (PGR) and the parity check target register (PCR), that is, the range that includes the fault that causes the fault detection indicator latch to turn on, is connected to the fault detection circuit. It is called the field of defense.

Conventionally, there is a method of automatically recognizing the coverage area of this fault detection circuit from logic design information. 100% of the faults that occur within the coverage area recognized by this method are detected by the fault detection circuit for the coverage area. That is, the failure detection display latch lights up.

Therefore, in the present invention, conversely, logic simulation is executed using verification data that causes a pseudo failure to occur in any specific portion within the coverage area of the failure detection circuit. The verification data used here recognizes the logic AND, OR, etc. gates, so that the signals connected to each logic are
Either a fixed or variable pattern can be determined, and when it is desired to generate a pseudo fault, by inverting the fixed signal, it becomes possible to create a pattern, and the combination of signals can also be limited.

In addition, the number of locations where pseudo failures occur is limited by targeting signals connected to registers, and due to execution time constraints in logic simulation,
This is a achievable number. Based on the results of the logic simulation performed in this way, it can be confirmed at the logic design stage whether the fault detection display latch lights up, that is, whether the fault detection circuit operates normally. As a result, if the check logic for fault detection is incorrect or otherwise inoperable, the logic of the fault detection circuit can be changed at the logic design stage.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a processing flowchart 1- of a simulation method of a failure detection circuit showing an embodiment of the present invention. Here, reference numeral 1 shows an outline of the procedure for simulating the failure detection circuit in this embodiment.

The input information is control information 10 and design information 20. The control information 10 includes auxiliary information necessary for identifying the fault detection circuit, information for controlling extraction of coverage areas, or information for controlling creation of verification data. The design information 20 is logical connection information of the target device, and indicates the connection relationship between parts constituting the device and the connection relationship between logical elements such as gates and latches in the parts. After executing the simulation of the fault detection circuit, the output information is checked in step 30 to see if the fault detection circuit operates normally, and if the fault detection circuit does not operate normally, the logic of the fault detection circuit in the design information 20 is This is design information 50 that has been fed back, such as making changes (step 40).

The design information 50 is completed by repeating the feedback of steps 30 to 40 for all fault detection circuits, and is more refined than the design information 20. The processing is performed by the range extraction processing section 200 of the failure detection circuit. It is roughly divided into an automatic verification data creation section 300 and a logic simulation section 400 . Conventionally, a fault detection circuit and its coverage area were manually recognized from design information, verification data was created, and logic simulation was executed, but in this embodiment, this is automated. Details of each process will be explained below.

FIG. 2 is a flowchart showing the processing procedure of the defensive range extraction processing section 200 in FIG.

The defense range extraction process will be explained below according to the flow shown in FIG.

First, the fault detection circuit is identified and the starting point and stopping point (end point) of the protection range are extracted from the input design information 20 (step 210). The fault detection circuit includes a fault detection display latch and a parity generator (PG).

It consists of a parity checker (PC) and other check circuits. A typical example is a parity generator (PG).
When using a parity checker (PC) and a parity checker (PC), as explained in Fig. 3, the start and stop points of the protection range are the fault detection indicator latch (CHK), parity generation target register (PGR), and parity checker, respectively. This is the target register (PCR).

Next, step 22 is to register the fault detection circuit as the starting point.
0), backtrace is started from the failure detection circuit which is the starting point, and the source elements of the target element are sequentially extracted (step 230). At this time, as in the conventional method, when the relevant element reaches the boundary point of the protection range of the fault detection circuit, that is, the stopping point (step 240), the 1~ race is completed for that element. If it is not a stopping point, the element is registered as being included in the field of defense (step 250). The process ends when all source elements reach a stopping point in some way (step 260).

The protection range is extracted by repeating the processing of steps 210 to 260 for all fault detection circuits.

FIG. 4 shows a conceptual diagram of the coverage area of the fault detection circuit. Here, 410 is a failure detection circuit, 411 is a coverage area of the failure detection circuit 410, 412 to 415 are replacement units, and 4, 16 and 417 are logical simulation starting points.

Logical simulation starting point 416 within defense range 411
, 417. This starting point can be freely specified as long as it is within the defense range, for example, control information 1 in Figure 1.
0, the starting point can be specified manually using the distance from the fault detection circuit 410 such as the number of gate stages or the number of latch stages, or the starting point can be specified for each fault detection circuit using random numbers.

Finally, verification data that causes a pseudo fault to occur at the logic simulation start points 416 and 417 is created (processing block 300), and the logic simulation is executed (processing block 400).

In the automatic verification data creation section 300, verification data can be manually designated using the control information 10, or random numbers can be generated using the built-in rule table according to the check logic, in the same way as when specifying the logical simulation start point. It is possible to automatically create verification data based on parameters such as distance from the fault detection circuit and distance from the fault detection circuit.

In this way, in this embodiment, the fault detection circuit and its check target logic circuit group are associated manually using a logic diagram, verification data is created, and the logic simulation (fault detection circuit operation By inputting the logic information file (confirmation), automatically recognizing the field of protection, creating verification data, and running logic simulations, the number of manual steps can be significantly reduced. Furthermore, it is possible to prevent deterioration in accuracy in checking the operation of the failure detection circuit due to errors caused by manual work by five people. Furthermore, since operation confirmation can be easily performed at the design stage, it is possible to facilitate logic changes in the case of inoperability and check logic changes to improve detection accuracy.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to automatically check the operation of a fault detection circuit by simply providing logical information of the target device and a small amount of supplementary control information, thereby reducing manual labor. The effect is a reduction of 70 to 80%. In addition, since errors caused by manual labor can be eliminated, the accuracy of operation confirmation is improved, which also makes feedback to logic design more accurate. This makes it possible to accurately compensate for defects that could not be detected due to insufficient verification of fault detection circuits in information processing equipment due to insufficient verification of fault detection circuits when faults occur on the user side, and enable fault recovery processing. This can contribute to shortening the work time.

[Brief explanation of the drawing]

FIG. 1 is a processing flowchart of a simulation method of a fault detection circuit showing an embodiment of the present invention, FIG. 2 is a processing flowchart of a range extraction processing section of the fault detection circuit in FIG. 1, and FIG. 3 is a processing flowchart of a parity generator. , a diagram showing an example of the use of a parity checker, and FIG. 4 is a diagram showing a conceptual diagram of a fault detection circuit and a target coverage area. ■ = Processing procedure of simulation method of fault detection circuit,
10: Control information, 20.50: Design information. 30: Operation check determination process, 40: Logic change process. 200: Protection range extraction processing unit of fault detection circuit, 300:
Verification data automatic creation processing section, 400: logic simulation section. agent

Claims (1)

[Claims] 1. In order to detect a fault that occurs during the operation of an information processing device, a fault detection circuit is detected (lit) at the logic design stage in response to a fault detection circuit built into the device.
In a logic simulation method for checking whether the fault detection circuit operates normally using verification data, the circuit receives logic design information of an information processing device as input and detects a fault from the logic design information; A means for automatically extracting a detectable area (coverage range) of a fault detection circuit including a circuit group (register group) to be detected by the fault detection circuit, and a means for automatically extracting verification data for confirming the operation of the fault detection circuit. and means for applying the verification data to a specific part within the coverage area of the fault detection circuit to execute a logic simulation to confirm whether or not the fault detection circuit operates normally. A simulation method for a fault detection circuit comprising: