JPH0290671A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To protect a semiconductor device against electrostatic breakdown at the implantation of impurity ion and to decrease contact resistance by a method wherein the introduction of n-type impurity into an ni side contact opening is performed through the diffusion from a PSG film and the introduction of p-type impurity into a p<+> side contact opening is executed through a PSG film or PSG, photoresist, and an interlaminar insulating film in a self-aligned manner. CONSTITUTION:After a photoresist 13 has been removed, a silicon oxide film 15 is deposited on the whole face through a CVD method, which is subjected to a heat treatment in an inert atmosphere, whereby boron ion-implanted into a p<+> diffusion region 7 is diffused into the inside of a substrate to form a p<+> diffusion region 17 and phosphorus is diffused from a PSG film 12 into the inside of a substrate through s polycrystalline silicon film 11 to form an n+ diffusion region 6 into an n<+> diffusion region 16. As the p<+> diffusion region 17 and the n<+> diffusion region 16 are formed in a self-aligned manner with openings 9 and 10, a leakage current is prevented from occurring due to the direct contact of an aluminum wiring 19 with a substrate 1 or an n well 2 even if the openings 9 and 10 are positionally deviated from the n+ diffusion region 6 and the p+ diffusion region 7 due to the mis-alignment in a photolithography process.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a semiconductor! The present invention relates to a method of manufacturing a four-product circuit, and particularly to a method of manufacturing a complementary semiconductor integrated circuit.

[Conventional technology]

Conventionally, the introduction of impurities in the manufacture of complementary semiconductor integrated circuits has consisted of two steps: photolithography and ion implantation. This is followed by a contact process in which openings are made in the interlayer insulating film on the p-type and p-type impurity diffusion regions formed on the surface of the semiconductor substrate, and the resist is removed only from the contact area in the n-type region, and arsenic, phosphorus, etc. The first photolithography introduces n-type impurities by ion implantation, the second photolithography introduces p-type impurities such as boron by ion implantation with only the contact portion of the n-type region removed, and the subsequent AiI The area consisted of the process of depositing the alloy.

[Problem to be solved by the invention]

The conventional impurity introduction method described above has the drawbacks that the process is long since two photolithography steps are performed, and that electrostatic damage is likely to occur when impurities are introduced by ion implantation.

[Means to solve the problem]

In the method for manufacturing a semiconductor integrated circuit of the present invention, p
a step of forming type and n-type diffusion regions; a step of covering the semiconductor substrate with an insulating film; and a step of selectively removing the insulating film on the p-type and n-type diffusion regions to form a contact opening. , a step of depositing a conductive mask material on the entire surface;
a step of depositing a silicate glass film containing phosphorus on the mask material; a step of selectively removing the silicate glass film in the contact formation portion of the n-type diffusion region using a resist mask; and a step of selectively removing the silicate glass film or introducing a p-type impurity into the n-type diffusion region using the resist as a mask;
A step of selectively removing the silicate glass film on the n-type diffusion region, and a heat treatment to remove phosphorus in the silicate glass film from the n-type diffusion region.
The method includes a step of thermally diffusing into the type diffusion region, and a step of forming wirings respectively connected to the p-type and n-type diffusion regions.

〔Example〕

FIGS. 1A to 1F are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), an n-well 2 is formed in a p-type crystalline silicon substrate 1 by a well-known method.

After forming the channel stopper 3 on the n-channel side and the channel stopper 4 on the n-channel side, field oxidation plA5 is formed using a selective oxidation method to decompose the element region.

Arsenic is introduced into the n" diffusion region 6, boron is diffused into the p+
A diffusion region 7 is formed. An interlayer insulating film 8 of borosilicate glass (hereinafter referred to as BPSG) is deposited on the surface, and
Contact openings 9 and 10 are provided on the +diffusion area 6 and the p+diffusion area 7.

Next, as shown in FIG. 1(b), a polycrystalline silicon film 11 is formed on the entire surface by low pressure chemical vapor deposition (LPGVD) to a thickness of 10 to 100 nm, and then phosphosilicate glass (hereinafter referred to as The film 12 (referred to as PSG) is grown by chemical vapor deposition (CV).
D) to a thickness of 100-200 nm.

Next, as shown in FIG. 1(C), p+
The PSG film 12 on the diffusion region 7 and its surroundings is removed, and the boron 14 is exposed to p+ using the same photoresist as a mask.
Diffusion region 7 and polycrystalline silicon! Ions are implanted into the surface of 11. Since the polycrystalline silicon film 11 has weak conductivity, electrostatic damage due to ion implantation is less likely to occur. Removal of the PSG film 1 and film 2 is performed with buffered hydrofluoric acid (a mixture of hydrofluoric acid and ammonium fluoride). At this time, the polycrystalline silicon M11 is FJ! Since the etching rate of ffj hydrofluoric acid is much lower than that of PSGfi, it acts as an etching stopper and reduces the interlayer insulation Jl! of BPSG. 8 is never exposed to the etching solution.

Next, as shown in FIG. 1(d), after removing the photoresist 13, a silicon oxide film 15 with a thickness of 1100 nm is deposited on the entire surface by CVD method, and p+ diffusion is performed by heat treatment in an inert atmosphere. In the region 7, the implanted boron is n'''', and in the diffusion region 6, it is PSGM! A1
Phosphorus is diffused into the substrate through the polycrystalline silicon film 11 from p+ diffusion regions 17 . An n+ diffusion region is formed.

Next, as shown in FIG. 1(e), the silicon oxide film 15
After removing the PSG film 1 with buffered hydrofluoric acid, an aluminum layer 18 is deposited on the entire surface.

Next, as shown in FIG. 1(f), the aluminum layer 18 is selectively etched by photolithography to form one aluminum wiring.

According to the above manufacturing method, since the 0+ diffusion region 16 and the p+ diffusion region 17 are formed in self-alignment with the openings 9 and 10, the openings 9 and 10 are formed in the n+ Diffusion region 6 and p+ diffusion region 7
Even if the aluminum wiring 19 and the silicon substrate 1 or the RL well 2 are deviated from each other, the aluminum wiring 19 and the silicon substrate 1 or the RL well 2 will not come into direct contact and leakage will not occur.

FIGS. 2(a) and 2(b) are cross-sectional views shown in order of steps for explaining a second embodiment of the present invention.

The difference from the first embodiment is that in this embodiment, the MOS
A polycrystalline silicon layer 21 doped with phosphorus serves as a gate electrode or wiring of an FET, and a second layer is formed on the first interlayer insulation WA8.
A tungsten silicide layer 22 is formed as a wiring layer, and a second interlayer insulator 823 of BPSG is further deposited to form an opening 24 on the tungsten silicide layer and on the polycrystalline silicon layer in addition to the opening 9°10. Openings 25 are formed using a well-known method, and these are connected to each other by A and &.For this reason, after forming the contact openings, tungsten silicide 26 and PSG film 27 are deposited on the entire surface. Then, the PSG film 27 on the opening 10 is removed by a photolithography process. Next, after spin-coding a silica film containing boron as an impurity or a polymer layer 28 having a boron-nitrogen skeleton, heat treatment is performed in an inert atmosphere to form a p" diffusion region 17 on the substrate surface of the opening 10.
An n+ diffusion region 16 is formed on the surface of the substrate in the opening 9 to solve the problem of the contact being pulled out due to misalignment of the metal during the photolithography process.

In this embodiment, phosphorus is introduced through the openings 24 and 25, and also serves to reduce the contact resistance between one aluminum interconnection, the tungsten silicide layer 22, and the polycrystalline silicon layer 21, which are formed simultaneously with the tungsten silicide layer 26, respectively. I am accomplishing it. Since the tungsten silicide H26 formed under the aluminum and serving as a mask material for etching the PSG film 27 is conductive,
Various wiring layers can be used, such as the contact resistance between the n+ and p+ diffusion regions 6, 7, the polycrystalline silicon layer 21, the tungsten silicide layer, and the aluminum wiring can be lowered without any problem.

〔Effect of the invention〕

As explained above, in the present invention, the n-type impurity is introduced into the n+ side contact opening by diffusion from the PSG film, and the n-type impurity is introduced into the p+ side contact opening through the PSG film.
By performing self-alignment between G or PSG, photoresist, and interlayer insulating film, the number of photolithography steps can be reduced to one, and the lower layer of the PSG film has conductivity and is resistant to etching of PSG. By applying a masking material such as polycrystalline silicon or silicide having 100% ions, it is effective to prevent electrostatic damage when introducing n-type impurities by ion implantation and to lower contact resistance.

6...n+ diffusion region, 7...p+ diffusion region, 8...
- Interlayer insulating film, 9, 10... opening, 10... element isolation region (silicon oxide film), 11... polycrystalline silicon layer, 12... PSG film, 13... photoresist,
14...Boron, 15...Silicon oxide film, 16.
...n+ diffusion region, 17...p" diffusion region, 18...
・Aluminum layer, 19... Aluminum wiring, 21
... polycrystalline silicon layer, 22 ... tungsten silicide layer, 23 ... second interlayer insulating film, 24.25.
...Opening, 27...Tungsten silicide layer, 2
6...PSG1%, 28...Polymer layer.

[Brief explanation of drawings]

FIGS. 1(a) to (f) and FIGS. 2(a) and (b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first and second embodiments of the present invention, respectively. .

Claims (1)

[Claims] forming p-type and n-type diffusion regions in the semiconductor substrate;
a step of covering the semiconductor substrate with an insulating film; and a step of covering the semiconductor substrate with an insulating film;
A step of selectively removing the insulating film on the mold diffusion region to form a contact opening, a step of depositing a conductive mask material over the entire surface, and a step of depositing a silicate glass film containing phosphorus on the mask material. selectively removing the silicate glass film in the contact forming portion of the p-type diffusion region using a resist mask; and adding p-type impurities to the p-type diffusion region using the silicate glass film or the resist as a mask. a step of selectively removing the silicate glass film on the p-type diffusion region; a step of thermally diffusing phosphorus in the silicate glass film into the n-type diffusion region by heat treatment;
1. A method of manufacturing a semiconductor integrated circuit, comprising the step of forming wirings connected to the type and n-type diffusion regions, respectively.