JPH0294A - Display device for character or the like - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a display device for displaying characters, etc., which has a scrolling function only within a specific column range or row.

BACKGROUND ART Conventionally, CRT display devices and the like have been equipped with a scrolling function that sequentially moves all character strings or all character lines on the screen upward or downward. It's convenient. In this way, the scrolling function.

It generally spans all columns or rows of the screen, so
In the case of scrolling, the displayed characters are shifted up one line at a time, and the characters displayed on the bottom line disappear from the screen, and newly displayed characters are always on the bottom line. Therefore, it is not possible to always display information only in a specific column or row, as when the scrolling function is turned off.

By the way, in general, although there are many cases where data display and guidance display, or certain data and comparison data, etc. are displayed at the same time and only one of them is desired to be scrolled, conventional technology does not allow the screen to be displayed in columns or The above requirement could not be achieved because it is not possible to divide the area by line and simultaneously use the area in two ways: an area with a scrolling function and an area without a scrolling function.

Objective: In order to satisfy this requirement, an object of the present invention is to provide a scrolling function only to a specific column range or a specific row range on the screen, display variable data in a display area having a scrolling function, The objective is to use the screen for multiple purposes by displaying fixed data in a display area that does not have a scrolling function. In other words, system guidance and operator guidance are displayed as fixed data.

To always display guidance even when a variable data display is scrolling.

Configuration The present invention sequentially counts and counts each line of the display screen.
Besides the row address counter that is up.

It has a scroll counter to get the row address in a particular scroll range, and inputs the output of the scroll counter to the memory row address input in the particular scroll range, and 1 outside the scroll range.
The output of a normal row address counter is switched to be input to the memory row address input, and an embodiment will be described below with reference to the drawings.

FIG. 1 is a block diagram of a CRT display device according to the present invention, showing the ordering of the scroll control circuit.

In FIG. 1, the shaded areas are the areas added according to the present invention.

When the clock (No. 1) generated by the timing generation circuit f is input to the digit address counter g, the counter g is counted up by this, and this value is input to the digit address counter g.
It becomes the digit address of refresh memory C via selector a.

The output of the digit address counter g is also connected to a horizontal synchronizing signal generating circuit j and a line counter h, and these circuits jp)1 generate a horizontal synchronizing signal H-8YNC and line No. 46 which is sent to the character generator d. occurs. The output of line counter h is the row address
Conventionally, the output of the 0 row address counter i, which is connected to the counter i and counts up the row address after counting one character line with the counter h, is sent to the refresh memory C via the row address selector b. However, in the present invention, a selector 1 is provided here to switch between the output from the scroll address generation circuit m and the output from the row address counter i, and to scroll a portion of the screen. is possible.

A vertical synchronizing signal generating circuit k is driven by the output of the row address counter i, and a vertical synchronizing signal v-8YNC is generated. Note that the output of the character generator d is converted from parallel to serial by a shift register e, and becomes a video signal VIDEO.

In the present invention, first, a case where only a specific column range is provided with a scrolling function will be described.

FIG. 2 is a screen display diagram of a conventional scrolling method, and FIG. 3 is a screen display diagram of a scrolling method according to the present invention. FIG. 2(a) shows the screen before scrolling, and the other screens show the screens after scrolling.

When scrolling using the conventional method, since the initial value of the first row address counter i itself is changed, each row is shifted up over the entire screen, and scrolling within a specific column range is difficult. I can't do it. Figure 2 (
In the state before scrolling in a), the character A is in the first line,
The letter B is displayed in sequence on the second line, and the letter O is displayed on the 15th line.
The letter B is displayed on the 16th line of 1.

Now, when the memory capacity for one display screen is the same as the display screen,
After scrolling, each line is shifted up by one line, and the letter A is displayed on the bottom line, as shown in FIG. 2(b). When the memory capacity is larger than the display screen, new data is displayed on the bottom line, and 16 lines before the latest data are always displayed on one screen.

The present invention allows scrolling only within a specific range, and allows any column range on the screen to be set as the scroll range.
Outside this scroll range, a constant display can always be maintained regardless of the scroll operation.

The state before scrolling is the same as that in FIG. 2(,), but the state after scrolling is as shown in FIG. 3(,)(b). FIG. 3(a) shows the case where the scroll range is from the first column to the 32nd column, and new data is displayed from the 1st column to the 32nd column of the 16th row. In this case, the right half of the display, that is, from the 33rd column to the 60th column, does not shift even after scrolling.

displayed on the same line. Further, FIG. 3(b) shows a case where the scroll range is from the second column to the 32nd column, and the scroll range can be made variable.

Figure 4 shows the circuit that performs the scrolling operation in Figure 3 (,), and Figures 5 to 5 show the operation time chart of that circuit.
It is shown in FIG. Furthermore, a circuit for performing the scrolling operation of FIG. 3(b) is shown in FIG. 9, and operation time charts of the circuit are shown in FIGS. 1O to 12.

FIG. 4 shows a conventional row address counter (ROWADD
RES C0UNTER (118 below) and memory row address selector (MEMORY ROW ADDR)
ESS (hereinafter omitted) is a block diagram showing a first embodiment circuit of the present invention inserted through a selector Sl.

In Figure 4, Sl is a selector, CI is a start address counter, C2 is a scroll counter, Gl, G2
is an inverter.

In the conventional method, the output of the row address counter (ROW
O~3) is directly entered into the memory row address input ROW O~3, and the initial value in the first row of the one-row address counter is changed during scrolling.

In the present invention, the output of the scroll counter C2 is given to the memory row address within the scroll range without changing the initial value of the one-row address counter.

Also, in Figure 4, the one-digit address counter (COL
UMN ADDRESS C0UNTER omitted)
When the output of inverter G1 is between O and 31, the output of inverter G1 is high.
level, and input B of selector Sl is selected. Input B of selector S1 is.

Connected to the output of scroll counter C2. This counter C2 is a 4-bit binary counter with 1
The next number after 5 becomes 0. In addition, this counter C2 is the display prohibition time (ROW4 is high level) including the vertical return time.
The output of the start address counter C1 is set as an initial value. This counter Ct also has O after 15.
It is a binary counter that is set to the initial value o by the system reset signal (SYSTEM RESET), and thereafter is set to the initial value o by the scroll command signal (SCRO
LL CMD).

5 to 8, FIGS. 5 and 6 are time charts for horizontal scanning, and FIGS. 7 and 8 are time charts for vertical scanning.

5 and 6, (,) is the clock of the digit address counter, and (b) is the CLM of the digit address counter.
O-CLM7, (c) is CLM of digit address counter
5=Sτ below, (d) is the ROWC of the row address counter
)-ROW4. (e) is QA-QD of scroll address counter C2, (f) is RO of memory row address
WO to ROW3 are shown.

In both FIGS. 7 and 8, (,) is the clock of the row address counter, and (b) is the R of the row address counter.
OWO~ROW4. (c) is QA-QD of start address counter C1, (d) is LOAD=ROW4 of scroll address counter, (e) is QA-QD of scroll address counter C2, (
f) is the memory row address ROWo-ROW3. (g)
indicates vertical blanking = ROW 4.

FIGS. 5 and 7 show the state before scrolling.

In Figure 5, from the first column (column address counter 0 in (b)) to the 32nd column (column address counter 31), the output (,) of the scroll address counter is the memory row address. (f), and from the 33rd column day to the 60th column day, the selector switches and the output (d) of the row address counter becomes the memory row address (f).

FIG. 5 shows the part where the row address counter (b) in FIG. 7 is O, that is, the horizontal scanning of the first row. The initial value 0 of c) is the scroll counter (d)
, and the first column always contains the scroll address.
The output (d) of the counter becomes 0.6 Figures 6 and 8 show the state after scrolling.

The output (c) of the start address counter is 1, and the output (,) of the scroll address counter is always 1 in the first row. Therefore, in FIG. 6, when displaying the first row, the memory row address (f) is 1 from the first column to the 32nd column, and the memory row address (f) is 1 before being scrolled. The data will be displayed. Between the 33rd column and the 60th column, the selector switches as before scrolling and outputs the row address counter (d).
becomes the memory row address, and the display contents do not change. Thereafter, the output of the start address counter is incremented before the scroll operation.

FIG. 9 is a block diagram of a second embodiment circuit in which the scroll range is variable by switching the JP line.
The P instruction sets the scroll range from the 2nd column to the 32nd column.

Sl is a selector, C1 is a start address counter, C2 is a scroll counter, Fl is a flip-flop, Gl, G3 are AND gates, G2. G4. G5
．． G6 is a NAND game 1-1 and G7 is an inverter.

JPI is a jumper for selecting the start address of the scroll range, and flip-flop F1 is set when the output of the digit address counter becomes the scroll start column. JP2 is a jumper for selecting the end address of the scroll range, and when the output of the digit address counter becomes the next value in the scroll end column, the flip-flop F1 is reset. Therefore, during the scroll range, the output of flip-flop F1 is at a high level, and input B of selector 31 is selected. Other operations are the same as in the case of FIG.

In this way, set the start address in JPI.

By setting the end address in JP2, you can select any scroll range.

Furthermore, instead of setting and resetting the flip-prop Fl by setting the scroll range using JPI and JP2 as shown in FIG. Of course, it is also possible to determine the address,
In this case, jumper wires JPI, JP2. gate circuit,
Flip-flop F1 becomes unnecessary.

10 and 11 are time charts during horizontal scanning, and FIG. 12 is time charts during vertical scanning. The state before scrolling during vertical scanning is the same as FIG. 7. (a
) to (g) are the same as those in No. 5 to FIG. 8.

Figures 13 and 14 are Figure 3 (,) of the present invention, respectively.
FIG. 3 is a screen display state diagram showing an application example of FIG. In Fig. 13, the data display is scrolled from the 1st column to the 32nd column, the guidance display is always displayed from the 33rd column to the 60th column, and even when the data display is updated by scrolling, the data display is displayed in the 33rd column. - Guidance is always displayed in the 60th column.

In addition, in Fig. 14, the first column and the 33rd to 60th columns are fixed areas, and the 2nd to 32nd columns are a scroll range.
The > mark is displayed for each line.

Next, a case will be described in which a scroll function is provided only to a specific line range on one screen.

FIG. 15 is a screen display diagram of the conventional scrolling method (same as FIG. 2), and FIG. 16 is a screen display diagram of the scrolling method according to the present invention.

Now, suppose that in FIG. 15(a) before scrolling, there is a case where it is desired to scroll the 1st to 14th lines without moving the display of the bottom two lines as they are.

In the conventional scrolling method, each row is shifted up as shown in FIG. 15(b).

The above requirements cannot be fulfilled.

In the present invention, any row range on the screen can be set as the scroll range, and the display outside the scroll range is always kept constant regardless of the scrolling operation.

FIG. 16(a) shows the state after scrolling, fjr11
This is a case where the scroll range is from the line date to the 14th line,
New data is displayed on the 14th line. Display X in the bottom two lines,
Y does not shift even after scrolling and is displayed on the same line.

Moreover, 16th [21(b) is the state after scrolling when the scroll range is from the 2nd line to the 14th line, and the new data is displayed on the 14th line. Display A on the first line and displays X and Y on the bottom two lines do not shift even after scrolling.
displayed on the same line.

The circuit that performs the scrolling operation shown in Fig. 16 (,) is the first circuit.
7, and its operation time charts are shown in FIGS. 18 and 19. Furthermore, the circuit that performs the scrolling operation of FIG. 16(b) is shown in FIG. 20, and its operation time is shown in FIG.
The charts are shown in FIGS. 21 and 22.

FIG. 17 shows a conventional row address counter (ROW A
FIG. 3 is a block diagram showing a third embodiment of the present invention, which is inserted between a DDRESS C0UNTER (hereinafter omitted) and a memory row address (hereinafter MEMORY ROW ADDRESS) through a selector;

St is a selector, C1 is a start address counter, C2 is a scroll counter, and 61 to G3 are NAND counters.
The gate G4 is a Noah gate, and G5 is an inverter.

When the output of the row address counter is between 0 and 13.

The output of gate G1 becomes high level, and selector S1
Input B of is selected. Input B of selector S1 is the output of scroll counter C2.

When the count value of this counter C2 reaches 14, the output of the NAND gate G2 becomes low level and returns to 0.

Further, this counter C2 is set to the output of the start address counter Ct as an initial value during the display inhibit time (ROW4 is at high level) including the vertical return time.

When this counter C1 also reaches a count value of 14, the output of the NAND gate G3 becomes low level and returns to C. The initial value of the start address counter C1 is set to 0 by the system reset signal (SYSTEM RESET), and thereafter, the start address counter C1 is set to 0 by the system reset signal (SYSTEM RESET).
OLLCMD).

Figures 18 and 19 are time charts showing the states before and after scrolling, in which (,) is the clock of the row address counter, and (b) is the RO of the row address counter.
WO~4, (c) is the start address counter C1
Q A” Q o, (d) is the scroll address
Counter LOAD=ROW4, (e) is scroll
QA of address counter C2 ” Q I), (f)
indicates memory row address ROWO~3, and (g) indicates vertical blanking ROW4.

In FIG. 18, from the 1st row (row address counter in (b) is 0) to the 14th row (row address counter is 13), the output (e,) of scroll address counter C2 is The memory row address (f) is the 15th
On the row day and the 16th row day, the selector S1 switches so that the output (b) of the row address counter becomes the memory row address (f
). The initial value 0 of the start address counter C1(c) changes to the scroll counter C2 within the display inhibit period.
(d) The output (e) of the scroll address counter C2 is always 0 for the first row.

In FIG. 19, the start address counter C
The output (c) of 1 is 1, and the output (e) of scroll address counter C2 is always 1 in the first row. Therefore, when the first row date is displayed (row address counter is O), the memory row address (f) becomes 1, and the data that was displayed on the second row before scrolling is displayed.

Similarly, the 14th line day display (line address counter is 13)
), the memory row address (f) becomes 0, and the data displayed in the first row before scrolling is displayed here. On the 15th and 16th row dates, as before scrolling, the selector S1 switches and the output (b) of the row address counter becomes the memory row address (f), and the display contents do not change. Thereafter, the output (c) of the start address counter C1 is incremented every time the scroll operation is performed, and becomes 0 after 13.

FIG. 20 is a block diagram of a fourth embodiment @ route in which the scroll range is variable from above the JP line cut, and the JP instruction in the figure sets the scroll range from the 2nd line to the 14th line. .

SL and 82 are selectors, D1 to D3 are decoders, CI is a start address counter, C2 is a scroll address counter, PL is a flip-flop, G1 is a NOR gate, and G2 is an inverter.

The output of the row address counter is ROWO~3.

It is decoded by decoder D3, and the start address of the scroll range is selected by JPI, and the next value of the end address is selected by JR2. During the scroll range, the output of flip-prop Fl becomes high level, and input B of selector S1 is selected.

Input B of selector S1 is the output of scroll address counter C2, and by selecting the next value of the end address with JP3, the start address is changed from JP5 via selector S2. It becomes a ring counter that counts sequentially within the scroll range. Similarly, start address counter C1 becomes a ring counter like counter C2 by selecting the next value of the end address with JP4. Therefore, by setting the start address of the scroll range for JPI, the end address for JP2 to JP4, and the start address for JP5 in binary, any scroll range can be selected.

(a) in the time charts of Figures 21 and 22
- (g) show the same things as (a) - (g) in Figs. 18 and 19.

For the 2nd to 14th rows in the scroll range, the output (e) of the scroll address counter C2 becomes the memory row address (f), and for the 15th to 1st rows, the row address
The output (b) of the counter becomes the memory row address (f). As shown in (e), the scroll address counter C2 becomes 1 after 13, and the data that was displayed on the 2nd line before scrolling is displayed on the 14th line.

Figures 23 and 24 are Figures 16 (, ) and (, respectively).
This shows an example of the application of b).

Figure 23 shows a data display that allows scrolling in the 1st to 14th lines, and a message that is always displayed as a guidance display in the 15th and 16th lines.
Even if the data display is updated by scrolling, the guidance is always displayed on the 15th and 16th lines.

Moreover, in FIG. 24, the 1st, 15th, and 16th lines are fixed areas, and the 2nd to 14th lines are a scroll range. On the first line.

Headings of data to be scrolled can be displayed, and tab set positions can also be displayed.

Effects As explained above, according to the present invention, it is possible to scroll only over a specific column range or a specific row range on the screen, and display messages, etc. other than constant data in a fixed area outside the scroll range. This allows the screen to be used for multiple purposes, and its range of applications is wide. Furthermore, a display device that can use a specific area within the same screen as a scroll range can be driven in the same way as conventional devices, and can be realized by simply adding a small amount of hardware to conventional circuits, so the effect is It's large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a CRT display device according to the present invention, FIG. 2 is a screen display diagram using a conventional scroll method, and FIG. 3 is a screen display diagram using a scroll method according to the present invention.
FIG. 4 is a block diagram showing the first embodiment circuit of the present invention, FIGS. 5 to 8 are operation time charts in FIG. 4,
FIG. 9 is a block diagram showing a second embodiment circuit of the present invention, FIGS. 10 to 12 are operation time charts in FIG. 9, and FIGS. FIG. 15 is a screen display diagram showing an application example, FIG. 15 is a screen display diagram using a conventional scrolling method, and FIG. 16 is a screen display diagram using a scrolling method according to the present invention. FIG. 17 is a block diagram showing a third embodiment of the present invention.
18 and 19 are the operation time chart in FIG. 17, FIG. 20 is a block diagram showing the fourth embodiment circuit, and FIGS. 21 and 22 are the operation time chart in FIG. 23 and 24 are screen display state diagrams showing an application example of FIG. 16 according to the present invention, respectively. Sl, S2: Selector, C1 new start address counter, C2 new roll address counter, Fl
: Flip-flop, D1~3: Decoder, JP1~
5 jumper wire to set the next value at the start or end of the scroll range. G: Gate.

Claims (1)

[Claims] (1) Obtaining the row address of a specific scroll range in a display device that has a row address counter that is counted up sequentially corresponding to each row on the display screen and a memory that uses the output of the row address counter as the row address. The output of the scroll counter is used as the memory row address only when the row address counter outputs a specific row range, and outside the specific row range, the output of the row address counter is used as the memory row address. A display device for displaying characters, etc., characterized by displaying line addresses.