JPH0131197B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a display control circuit for performing multi-window display.

<Prior art> When using one display device as n screens (windows), it has conventionally been necessary to divide the screen as shown in Figure 1a, or overlap the windows as shown in Figure 1b. There are known ways to do this. However, in conventional display circuits, the contents of the image information memory must be the same as the display screen, and the image information memory must be rewritten to make changes such as changing the division position or reversing the overlapping. It was necessary and took a very long time.

<Object of the Invention> The present invention has been made for the purpose of solving the above-mentioned problems of the conventional art. The display is superimposed on any position on the screen, and the priority order of superimposition can be changed freely and instantaneously using a program. Furthermore, operations such as moving or changing the size of a window, or changing the image information in the window to another area of the image information memory can be performed instantly using a program.

<Embodiment> As shown in FIG. 3, a conventional display circuit consists of an address counter 1, an image information memory 2, a display timing circuit 3, and a horizontal/vertical timing circuit 4 (5 is a display, 6 is a bus line). ), the contents of the image information memory indicated in order by the address counter are displayed on the display under timing control. In this way, the address counter only shows the image information memory in order, so if you want to display a display screen like the one shown in Figure 1 a and b, the contents of the image information memory must of course be the same as the display screen. Nakatsuta.

In the present invention, as shown in FIG. 2, the image information memory need not be the same as the display screen, and parts of the image information memory can be displayed by superimposing them.

The present invention is realized by placing an address conversion circuit 7 between a conventional address counter 1 and an image information memory 2 as shown in FIG. That is,
Rather than sequentially showing the image information memory as in the past, the idea is to arbitrarily convert the address indicating the image information memory to indicate and display an arbitrary location in the image information memory.

If this address conversion circuit is depicted in a little more detail, it will be as shown in FIG. Here, the mechanism of address conversion will be explained with reference to FIG. 6 (a in the figure shows the contents of the image information memory, and b shows the display screen). In a conventional display circuit, when the display start address is SAD, the address counter 1 outputs from the display start address SAD to the display end address SED, which is the end of one screen display.
This address data from SAD to SED is supplied as is to the image information memory 2, and
Only the area corresponding to the display screen (the area above the dotted line of the image information memory in FIG. 6) is displayed as is. Therefore, the present invention is as shown in FIG. 6a.
In the state of the image information memory 2, in order to display as shown in FIG.
When the start position to be displayed on the display screen (this address is designated as a) is addressed, it is sufficient to change the address to the address a' of the start position of the data area A in FIG. 6a, that is, convert the address.

That is, when displaying data area A at a position on the display screen that corresponds to data area B of image information memory 2, the first address at which data area A on the display screen is to be displayed is set to a (the address a is (corresponds to the start address of data area B)
Let the start address of the data area A of the image information memory 2 be a'. Further, it is assumed that a'-a=d, where d is a bias value held in a bias value register to be described later. Here, when the address counter starts from SAD and reaches a, if we add the bias value α, a + α = a', and the contents of area A are displayed in area B, resulting in the display screen shown in Figure 6. . However, with this alone, there is no boundary information indicating the extent of area A, so the display screen only displays area A and one screen around it.

Therefore, in order to determine the boundary, the column address counter 11, column map RAM 12, row address counter 13, row map RAM 14, priority register 15, and window selection circuit 16 shown in FIG. 5 are provided. The column address counter 11 is a counter that counts the horizontal direction of the display screen using the display clock DISPCLOCK as a counter clock signal and the horizontal and vertical BLANK signals as reset signals. On the other hand, the row address counter 13 is a counter that counts the vertical direction of the display screen using the horizontal and vertical BLANK signals as clock signals and the vertical synchronization signal (VSYNC) as a reset signal. Also column map RAM1
2. The two RAMs of the row map RAM 14 horizontally and horizontally mark the boundaries of each window _W0 to _W3 as shown in FIG.
This is a screen boundary memory that is divided vertically and stores "1" at the divided positions. In the embodiment, the column map RAM 12 and the row map RAM of the screen boundary memory
Reference numeral 14 is provided with memories corresponding to windows W ₀ to _{W 3} , respectively, and can be divided into four at most. The window selection circuit 16 is constructed as shown in FIG. T flip-flops 21 and 22 receive data from the column/row map RAM, Row MAP Data,
Column MAP Data becomes 1 and the output Q remains 1 until the next 1 comes. next 23
The AND gate is configured so that the outputs of 21 and 22 are both 1, that is, the area of each window in FIG. When there are four windows, four sets of 21 to 23 are required. When passing through the above circuit, multiple windows may overlap in some parts. Here, 24 priority circuits determine the top and bottom of the stack according to the priorities specified by the 15 priority registers. Through the priority circuit, at most one window is selected at a given moment, and the selected window number
Bias registers 17 ₀ to 17 ₃ corresponding to S ₀ to S ₃
is selected by the multiplexer 18, and the stored contents of the bias values α ₀ to _{α 3} are added to the address a from the address counter at the previous stage (full adder 19
), the address becomes address a', which indicates the image information memory, and a window is displayed.

9 and 10 show the correspondence between the priority register a and the display screen b. If there are 4 windows, priority register 15
requires 2 bits x 4 = 8 bits, and if we decide from the lowest priority to 00, 01, 10, 11, the priority order in Figure 9 is W ₀ < W ₁ < W ₂ < W ₃ . Therefore, the display screen becomes as shown in figure b, and even if the boundaries are the same, in figure 10 W ₀ > W ₁ > W ₂
> _W3 , so the display screen will be different from that shown in Figure 9.

Here, to simplify the explanation, the number of windows is 4.
However, it is possible to use any number of windows.

In FIG. 5, the column map RAM 12, row map RAM 14, priority register 15, and bias registers ₁₇₀ to ₁₇₃ can be freely rewritten by the program, so you can move the window, change the size, and change the top and bottom of the stack of windows. Since the replacement can be done without rewriting the image information memory, it can be done instantly.

With the above hardware, it is possible to work on the display screen with many books, drawings, and report sheets placed on the desk, and the flexibility and usage efficiency of the display screen and image information memory are improved. It is measured.

The present invention can be applied to both character displays and bitmap displays, and can also be applied to display devices such as CRTs (cathode ray tubes),
Can be used for EL, plasma displays, etc.

<Effect> 1 To specify the position and size of one window, you only need to write up to four points in the screen boundary memory, and you can instantly move and change the size of the window.

2. By simply specifying the priority order in the priority register, you can instantly change the upper and lower priority order of stacked windows.

3 Address conversion can be performed simply by specifying a bias value for address conversion in a register called a bias register, and since the bias register can be freely rewritten, the window display area of the image information memory can be moved freely and instantaneously.

4. The degree of freedom of the screen is improved and the efficiency of use of image information memory is improved.

[Brief explanation of drawings]

FIGS. 1a and 1b are diagrams showing examples of multi-window display. FIG. 2 is a diagram for explaining the present invention, in which a shows the contents of the image information memory, and b shows the display screen. FIG. 3 is a block diagram showing a conventional display circuit. FIG. 4 is a block diagram showing a display circuit according to the present invention. FIG. 5 is a block diagram showing a specific configuration of the address translation circuit shown in FIG. 4. FIG. 6 is a diagram for explaining address conversion, in which a shows the contents of the image information memory and b shows the display screen. Figure 7 shows the column and row map RAM shown in Figure 5.
FIG. FIG. 8 is a block diagram showing a specific configuration of the window selection circuit 16 shown in FIG. 5. FIGS. 9 and 10 are diagrams for explaining the correspondence between the contents of the priority register and the display screen. Explanation of symbols, 1: Address counter, 2: Image information memory, 3: Display timing circuit, 4: Horizontal/vertical timing circuit, 5: Display, 6: Bus line, 7: Address conversion circuit, 11: Column address counter, 12 : Column map RAM, 13: Row address counter, 14: Row map RAM, 1
5: Priority register, 16: Window selection circuit, ₁₇₀ , ~ ₁₇₃ : Bias register,
18: multiplexer, 19: full adder, 21,
22: T flip-flop, 23: AND gate, 24: priority circuit.

Claims (1)

[Scope of Claims] 1. In a screen split display in which image information in an image information memory is sequentially read out by an address counter and displayed in each window on a display screen divided into a plurality of areas (windows), a predetermined area of the display screen is displayed. In order to display a predetermined image information area held in the image information memory at the window position, the address value of the address counter is read from the image information area of the image information memory corresponding to the window in synchronization with display scanning. an address conversion circuit for controlling the conversion to be output, a rewritable column map memory for storing the horizontal (column direction) divided screen boundary position for each of the windows of a display screen divided into a plurality of windows, and its vertical direction ( a screen boundary memory including a rewritable line map memory for storing divided screen boundary positions (in the row direction), and the address conversion circuit determines the priority of each window in a portion where a plurality of windows overlap on the display screen. A window selection signal is generated in accordance with a designated priority memory, screen boundary information read from the screen boundary memory in synchronization with horizontal/vertical scanning signals of the display screen, and window priority information from the priority memory. The output window selection means associates each window of the display screen divided into a plurality of windows with the image information area of the image information memory to be displayed in the window, and positions each image information area in the corresponding window. It is equipped with a rewritable bias value memory that stores the bias value of
Based on a window selection signal output from the window selection means in synchronization with the scanning signal of the display screen, a bias value corresponding to the selected window is retrieved from the bias value memory, and the bias value is read from the address counter. The address value is added to the address value to perform address conversion, and the address value output from this address conversion circuit is used to read out the image information memory, displaying a predetermined image information area of the image information memory in a predetermined window position on the screen, and displaying a plurality of A screen splitting control device that displays overlapping windows according to the priority order of the windows.