JPH0296331A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a semiconductor device and a method for manufacturing the same.

Recently, CV D (Chew+1cal Vapor
For example, tungsten (W) is
A new technique called CVD-W is known, which is a technique of depositing high-melting point metals such as (for example, using this as wiring).

There are roughly two ways to use this CVD-W. That is, the first method is the so-called S el
It is called ``active-W'' and is used for contact holes, etc.
A layer of W (barrier metal) is selectively formed only on the exposed portion of i, and this W layer plays the role of, for example, forming an ohmic contact. In this case, a layer such as A1 is formed on the W layer as a wiring.

The second method is so-called B 1anket-W, in which wl is deposited over the entire surface of the wafer including contact holes, etc., and this WN is then used as wiring by performing predetermined patterning. In addition,
In this case, in order to improve the adhesion between the base (St, 2 layer, and 31 substrate described later) and WN, TLW or the like is thinly deposited on the entire surface by CVD or sputtering, and patterned in the same manner as above. It forms an adhesive layer that will be described later.

Next, for Figure 5, 5elective-W and 6th
The manufacturing process of B1anket-W will be explained with reference to the figures.

First, as shown in FIG. 5A, an N-type semiconductor region 2 is diffused in advance in a P-type silicon substrate 1, and a stow layer (JiIISf1) is formed on the entire surface including this semiconductor region 2.
After depositing the wA edge film 3 by CvD, predetermined contact holes 4 are formed as shown in FIG. 5B.

Then, as shown in FIG. 5C, for example, WF, /H.

is supplied, W is selectively deposited in the contact hole 4 to a predetermined depth by CVD to form the W layer 5, and then the fifth layer 5 is formed.
Affi is applied to the entire surface including contact hole 4 as shown in figure D.
6 is applied.

Next, as shown in FIG. 5E, a predetermined area is covered with, for example, a photoresist 10, and a predetermined patterning is performed as shown in FIG. 5F. Wiring 6 is formed.

As a result of various studies conducted by the inventor of the present invention regarding devices obtained by the manufacturing process as described above, the following problems were found.

(1), i.e., WF&/H! When W5 is deposited in the contact hole 4 using gas, the St exposed in the contact hole is consumed (halides of high melting point metals such as W halogenate and eat Si through their reduction reaction). 2), W5 may enter the N+ type semiconductor region 2. And W
When reaches the P-type silicon substrate 1 (even if it does not reach the P-type silicon substrate 1,
For example, the junction characteristics of the PN junction deteriorate. ) There is a problem in that leakage current occurs in a junction region such as a PN junction.

(2) Also, this W5 deposition is carried out in the contact hole 4.
A deep contact hole (for example, 1.0 μm in diameter)
(with a depth of about 1.0 μm), the time required for deposition becomes longer, reducing productivity or throughput (T
There also arises the problem of a decrease in throughput.

Next, B1anket-W will be explained. First, as shown in FIGS. 6A and 6B, contact holes 4 are formed through the same process as the example in FIG. 5.

Next, as shown in FIG. 6C, TiW, for example, is deposited on the entire surface including the contact hole 4 by CVD to a thickness of 1000 Å.
The following relatively thin adhesive layer 7 is formed, and as shown in FIG.
deposit.

Next, as shown in FIG. 6E, a predetermined area is covered with, for example, a photoresist 20, and predetermined patterning is performed to form a sixth photoresist.
Form a W pattern &'19 as shown in Figure F.

That is, as a result of the inventor's various studies regarding the device obtained by the manufacturing process as shown in FIG. 6 above,
The problems are shown below.

(1) Although omitted in the above figure, photoresist)
When exposing, developing and patterning 20, the surface of the base W9 deposited by the CVD method is rough as shown in 21, so the alignment of the exposure mask is misaligned, and the light during exposure is transferred to W9. The light is diffusely reflected on the surface 21.

As a result, the pattern corresponding to the mask could not be exposed.
There is a problem in that the photoresist 20 deviates from the designed pattern and the W9 deforms from the intended pattern, making it difficult to miniaturize.

(2) Furthermore, when etching W9 in FIGS. 6E and 6F, the surface roughness remains as it is on the underlying Si01.
Sin is transferred onto the layer 3, causing the surface of the layer 3 to become rough. In other words, since the surface of W9 has unevenness, it is not possible to machine and notch uniformly, and the surface of W9 is rough.
Residues of adhesive layer 7 and W9 remain on layer 13.

When attempting to remove this residue by etching, S
Even the iO□ layer 3 is etched. Furthermore, when considering the entire wafer, there is a difference in film thickness w9 (for example, if the film thickness near the center of the wafer is about 1 μm, the film thickness near the periphery is about 0.7 μm). This makes it difficult to perform uniform etching, which further exacerbates the above-mentioned problem.

(3) Also, when etching W9, for example, SF.

When etching is performed using a gas such as NF or NF, the etching by these gases is isotropic, so the area directly under the resist is also etched, creating an undercant, and as a result, the width of the wiring 9 becomes wider than the design value. It becomes thinner.

As is clear from the above, the S of the first method
In the case of elective-W, the wiring in the device obtained by the manufacturing process shown in Fig. 5 is mainly A2.
In addition to requiring etching, the above-mentioned 2
Two problems arise.

In the case of the second method, Blanket-W, the wiring in the device obtained by the manufacturing process shown in FIG. 6 is mainly made of W, but etching of W is also required in this case. Furthermore, etching of W is very difficult and requires a new etching technique, which makes it extremely difficult to solve the above-mentioned problems and is also disadvantageous for miniaturization.

Objective of the Invention The objective of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can easily obtain a wiring pattern of a desired pattern, is compatible with miniaturization, and has excellent productivity and reliability. be.

21 Structure of the Invention That is, the present invention provides a wiring structure consisting of an adhesive layer formed in a predetermined pattern on the whole surface of a semiconductor substrate, and a main wiring layer formed only on this adhesive layer in a self-aligned manner. The present invention relates to a semiconductor device having the following.

The present invention also provides a method for manufacturing the semiconductor device, including a step of forming an adhesive layer on the entire surface of a semiconductor substrate, a step of patterning this adhesive layer, and a step of forming an adhesive layer on the patterned adhesive layer. The present invention also provides a method for manufacturing a semiconductor device π, which includes a step of forming a main wiring layer in a self-aligned manner following the pattern of the semiconductor device π.

The thickness of the adhesive layer is 1000 Å or less, especially 100 Å or less.
The number may be 1,000 to 1,000 people, preferably 500 to 600 people. Further, the thickness of the main wiring layer is 3000 Å or more,
In particular, the number may be 3,000 to 20,000, preferably 5.
000 to 10,000 people.

E, Example The present invention will be explained in detail below.

1 to 3 show an embodiment in which the present invention is applied to, for example, a mask ROM.

In the device according to this example, as shown in FIG. 1, an N+ type diffusion region (drain region) 22 is formed in a P type silicon substrate 1, and an S tOzN 3 is formed, and further a predetermined contact hole 4 is formed. Then, S L Oz ji including this contact hole 4
On iB, a predetermined pattern of adhesive N (for example, TiW) 1 is applied.
1 is formed, and furthermore, only on this adhesive layer 11 is C.
Main wiring N (for example, W) 12 in a self-aligned manner by VD
is formed.

The mask ROM (metal ROM) 8 will now be described. It is constructed as shown in FIG. They are formed in the same pattern and programmed to determine whether or not to connect the drain to the bit line B (wiring) at the final stage of device manufacturing (ie, metal wiring A). Wl and W2 in the figure are word lines. When a connection is made with the metal wiring 12, a transistor is formed, but when there is no connection (the drain is in an electrically floating state), it is equivalent to not forming a transistor.

Here, the bit line B and the wiring 12 can have the wiring structure shown in FIG. That is, as shown in FIG. 1, since the adhesive layer 11 of a predetermined pattern is formed and the main wiring layer 12 is formed only on this adhesive layer in a self-aligned manner, there is no need to etch the metal 12 of the main wiring. Wiring in a desired pattern can be easily obtained, which is advantageous for miniaturization.

Next, a method for manufacturing a semiconductor device according to this embodiment will be explained with reference to FIG.

The steps shown in FIGS. 3A to 3C are almost the same as the steps shown in FIGS. 6A to 6C, so the explanation thereof will be omitted.

Next, as shown in FIG.
As shown in the figure, the adhesive layer (e.g. T i W : thickness 1
00-1000 people, more preferably 500-600 people)
11 in a predetermined pattern. Then, as shown in FIG. 3F, a W layer (main wiring layer: thickness 3,000 to 20,000 layers, more preferably 5,000 to 10,000 layers) is formed on the adhesive layer 11 by the CVD Selective-W method, following the pattern. ) 12 in a self-aligned manner.

As is clear from the manufacturing process described above, in the device and its manufacturing method according to this example, W12 is deposited in the same pattern on the adhesive layer 11 by simply depositing W by CVD as shown in FIG. 3F. (adhesive layer 1
(W is not attached where there is no 1), there is no need to etch the metal (W wiring), and it is sufficient to etch the very flat and thin adhesive layer 11 (see FIG. 3E).

Therefore, devices can be easily manufactured using conventional etching techniques without requiring any new techniques.

Therefore, it is only necessary to etch the adhesive layer 11, which has a very flat surface.
n. The problem of layer roughness does not occur, and undercuts can also be almost eliminated.

Furthermore, since the exposed St (i.e., the N-type diffusion region 22) at the bottom of the contact 4 is covered with the adhesive layer 11, Si is not consumed when depositing W, which is caused by the destruction of the PN junction. There is no need to worry about leakage current.

Furthermore, since the inside of the contact 4 is covered with the adhesive layer (TiW) 11, the growth of W12 starts not only from the bottom of the contact 4 but also from its sidewalls.

Therefore, the time required to deposit W can be shortened. actually,
For a contact hole with a diameter of 1 μm and a depth of 1 μm, the time required to deposit W when there is an adhesive layer is about half that when there is no adhesive layer.

FIG. 4 shows another embodiment, which is substantially the same as the example shown in FIG. 1 except that no contact hole is formed.

That is, a Sto layer 3 is formed on a P-type silicon substrate 1, an adhesive layer 11 is formed in a predetermined pattern on this Sin layer, and then only on this adhesive layer 11 in the same manner as described above. A main wiring layer (W) 12 is formed in a self-aligned manner.

Therefore, there are advantages similar to those of the first embodiment described above, and device miniaturization can also be promoted. Furthermore, the structure shown in FIG. 4 can of course be adopted for so-called multilayer wiring.

Although the present invention has been illustrated above, the above-mentioned example can be further modified based on the technical idea of the present invention.

For example, the pattern of the above-mentioned adhesive layer and the main wiring layer on the adhesive layer can be modified in various ways, and the material of the adhesive layer can be made of an appropriate material (for example, the adhesive layer can be made of W S t z , Ti/W, polysilicon, etc., or the main wiring layer can be made of The layer may be made of tungsten silicide, etc.).

Further, as the method for forming the adhesive layer and the main wiring layer described above, other than CVD, an appropriate method such as a suvafuta method can be adopted. In addition,
In addition to the above-mentioned devices, the present invention also applies to devices such as RAM (Ra
Of course, the present invention can also be applied to a wide range of applications such as 2018-2012 (Access Memory), etc., and its application range is wide, and the application location may be any location where a wiring layer is formed.

1. Effects of the Invention As described above, the present invention configures the wiring by forming the main wiring layer in a self-aligned manner only on the adhesive layer formed in a predetermined pattern, so patterning of the main wiring layer is unnecessary. Then,
Wiring in a desired pattern can be easily obtained. Moreover, there is no misalignment of the mask alignment (therefore, it is possible to miniaturize the semiconductor device, and since the adhesive layer is provided on the base, the consumption of semiconductor material is prevented, and the formation of the main wiring layer is easy. becomes.

[Brief explanation of the drawing]

1 to 4 show embodiments of the present invention. FIG. 1 is a cross-sectional view of the main part of a mask ROM (1
2 (A) is a plan view of the main part of the mask ROM, and FIG. 2 (B
) are the equivalent circuit diagrams, Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E,
3F is a cross-sectional view sequentially showing the main steps of the method for manufacturing the device shown in FIG. 1, and FIG. 4 is a cross-sectional view of another example of the device. 5 and 6 show conventional examples, and 5A
Fig. 5B, Fig. 5C, Fig. 5D, Fig. 5E, Fig. 5F
The figures are cross-sectional views sequentially showing the main steps of the device manufacturing method by Selective-W, Figures 6A, 6B, 6C, 6D, 6E,
FIG. 6F is a cross-sectional view sequentially showing the main steps of the device manufacturing method using B1anket-W. In addition, in the symbols shown in the drawings, 1...semiconductor substrate (P-type semiconductor substrate) 2.2
2...N medium-sized semiconductor region (drain region) 3
... Insulating layer (SiOx layer) 4 ... Contact hole 5 ... W layer 6.9.12 Main wiring layer CAl or W) 7.11 ... Adhesive layer (TiW) B . . . Bit lines Wl, W2 . . . Word lines.

Claims (1)

[Scope of Claims] 1. A wiring comprising an adhesive layer formed in a predetermined pattern on one main surface of a semiconductor substrate, and a main wiring layer formed in a self-aligned manner only on this adhesive layer. Semiconductor equipment. 2. Forming an adhesive layer on one main surface of the semiconductor substrate;
A method for manufacturing a semiconductor device comprising the steps of patterning the adhesive layer and forming a main wiring layer on the patterned adhesive layer in a self-aligned manner following the pattern of the adhesive layer.