JPH03100833A - Virtual machine control system - Google Patents

Abstract

PURPOSE:To inform a host of an I/O interruption corresponding to an I/O instruction by securing such a constitution where the host produces the I/O instruction with use of a domain and at the same time controls the value of the queue selection information. CONSTITUTION:A host hardware interruption queue 41 is provided together with a gust hardware interruption queue 42, a physical subchannel 52 containing a domain identifier and the interruption queue selection information, an input/ output processor 4, and the channels 5. The processor 4 checks the interruption queue selection information when the end of an input/output process is informed from the channel 5. Then the processor 4 connects the subchannel 52 to the queue 41 when the contents of the interruption queue selection information have the prescribed value. If the contents are not equal to the prescribed value, the subchannel 52 is connected to the queue 42 designated by the domain identifier of the subchannel 52. In such a constitution, an I/O interruption corresponding to an I/O instruction is informed to the host.

Description

Detailed Description of the Invention (Summary) Regarding the input/output control method of a virtual machine, the host can issue the I10 instruction using the domain of the guest, and by controlling the value of the interrupt queue selection information, the above I10 instruction can be issued. The purpose is to be able to notify the host of the 110 interrupt corresponding to 1. Interrupt queue selection information is provided in the guest subchannel so that the interrupt queue selection information can be changed from the host, and when the contents of the interrupt queue selection information are a predetermined value,
This allows interrupt conditions caused by the subchannel to be submitted to the host's interrupt queue instead of to the guest's interrupt queue specified by the domain identifier of the subchannel.

[Industrial application field]

The present invention relates to a virtual computer control method, particularly an input/output control method.

[Conventional technology]

First, the general configuration of the virtual machine will be described with reference to FIGS. 6 and 7. FIG. 6 is a diagram showing the configuration of a virtual computer system. The purpose of the virtual computer mechanism is to provide a virtual real computer environment using a single piece of hardware to a plurality of users (O8).

The hardware configuration is the same as a conventional computer system.

The virtual machine mechanism has three main components. A virtual machine control program (hereinafter referred to as a host program or simply a host) sequentially starts a virtual machine (hereinafter referred to as a guest program or simply a guest) in a time-sharing manner. )
Start l.

After the time slice assigned to guest 1 has elapsed, the next guest is activated as guest 22, then guest 3, and so on. This approach allows multiple operating systems to run on a single piece of hardware.

As mentioned above, since a single piece of hardware is shared by multiple guests, the system resources used only by that guest (
The guest may use the console (such as a console) without permission, but the guest cannot freely operate resources (such as a physical CPU) that are shared between guests. Therefore, the host intervenes in the control of the guest when it is necessary to manipulate system shared resources.

FIG. 7 is a diagram showing the flow of processing when a system operation command is issued. The guest is a virtual machine, but most instructions can be executed directly without host intervention. If the command issued by the guest is a system resource manipulation command and requires host intervention, "instruction interception" occurs at the time the command is issued, and control is transferred to the host. .Similarly,
“Delegating control to the host using an interrupt as a trigger”
It is called ``Interrupt Interception'' (interrupt intercept). Therefore, in order to run a guest program at high speed, it is necessary to transfer control of the physical CPU from the host to the guest. Hardware with a virtual machine support mechanism has additional instructions for this purpose. This command is E
X V M (Execute Virtual M
It is called achine). The transfer of control rights between the host and the guest by the EXVM command and command/interrupt is shown in FIG.

By the way, in a virtual computer system, the same functions and environment as those running on a real computer are provided to the virtual computer running on it, without making the virtual computer aware that it is running in a guest environment. is required to do. This also applies to I10 processing. In existing virtual machine systems, interrupts for I10 instructions issued by a guest are reported to the guest, so if an interrupt cannot be caused to the guest, the host uses a subchannel within its own domain. An I10 instruction was required to be issued. The case where an interrupt cannot be caused to a guest refers to when the host newly establishes a guest, or when the host emulates an I10 instruction that does not involve an interrupt issued by the guest by using an I10 instruction that involves an interrupt. Specifically, in the former case, the I10 supervisor of the guest does not exist, so it is not possible to interrupt the guest, and in the latter case, for example, the host cannot issue a channel reset command issued by the guest. When emulating with normal channel commands, this interrupt should not be reported to the guest because the guest does not expect the interrupt that normal channel commands generate.

FIG. 4 is a diagram illustrating interrupt management in a conventional computer system. In the figure, 4 is an I10 processor, 11 is a host CPU, 12 is a guest CPU,
31 and 32 are hardware interrupt masks, 41 and 42 are interrupt queues, 51 and 52 are physical subchannels, 61 and 62 are domain identifiers (ID), Pi is a host, and P2 is a guest, respectively.

A hardware interrupt mask 31 is provided corresponding to the host CPU 11, and a hardware interrupt mask 32 is provided corresponding to the guest CPU 12. The hardware interrupt mask has a plurality of bits, and when the bit value is 1, an interrupt request of the corresponding class is accepted. The hardware interrupt queue 41 is the host CPU
I1, and the hardware interrupt queue 42 corresponds to the guest CPtJ12. Each entry in the hardware interrupt queue has a one-to-one correspondence with each bit in the hardware interrupt mask, and interrupt requests of each class are queued. The I10 processor 4 performs I10 processing and has a function of distributing interrupt requests to the host or each guest. In the illustrated example, subchannel 51 resides in host P1 and subchannel 52 resides in guest P2. The subchannels correspond to I10 devices.

A domain identifier 61 exists in the subchannel 51, and a domain identifier 62 exists in the subchannel 62. In the domain identifier, the identifier of the domain that holds the subchannel to which it belongs is written. Domain A is a main memory section assigned to host P1, and domain B is a main memory section assigned to guest P2. If so, the subchannel 52 is connected to the interrupt queue 42 by the I10 processor 4, and the completion of the I10 processing is reported to the guest CPU 12 via the interrupt mask 32.

FIG. 5 is a diagram showing I10 activation→I10 processing→interrupt report in the conventional system. In the figure, 1 is a host space, 2 is a guest space, 5 is a channel, 6 is a memory control device, 7 is a main storage device, 30 is a hardware interrupt mask, 53 is a physical subchannel, 63 is a domain identifier, 1
01 is control information, 201 is channel control word (CCW),
301 indicates data.

There is a hardware specific area in the main storage device 7.
This hardware-specific area contains a hardware interrupt queue 41 for domain A. A hardware interrupt queue 42 and physical subchannels 51 to 53 for domain B are provided. Host space (domain A) 1 is host P1
The guest space (domain B) is a partition where the program of guest P2 is stored.

Referring to Figure 5, I10 startup in the conventional method → I10
Processing→Explain interrupt reporting.

(2) The host CPU II issues an I10 activation command using the subchannel number and the storage address of control information (CCW address, etc.) as operands. The contents of the control information are reflected in the physical subchannel 51 by hardware or software for the subsequent step 10100.

■ Channel 5 uses physical subchannels and communicates I1 with data space 301 according to channel control word 201.
Perform 0 processing.

(2) Channel 5 notifies the end of I10 processing by interrupt. The I10 processor 4 looks at the content of the domain identifier 61 written in the physical subchannel 51, connects the physical subchannel to the interrupt queue 41 for domain A, and sends the host CPt through the hardware interrupt mask 30.
Reports the interrupt condition to J11.

(2) The host CPtJ11 takes in interrupt information from the physical subchannel 51 connected to the hardware interrupt queue, and performs the corresponding interrupt processing.

In the conventional method, in order not to interrupt the guest when the guest issues a channel reset command, etc., the control information and C
CW, it is necessary to write data, and the amount of host space 1 consumed increases.

[Problem to be solved by the invention]

As mentioned above, in the conventional method, an interrupt for a guest I10 instruction issued using a guest's domain is reported only for that guest, so an I10 instruction that cannot cause an interrupt for a guest all required hosts to issue using their own domain.

However, in order to achieve flexible control in which the host issues I10 instructions using the guest's domain, it is necessary to be able to issue I10 instructions to the guest's storage space even under the above circumstances. - Although subchannels can be transferred to the host space, they cannot be transferred to the guest space.

The present invention was created in view of this point, and allows the host to issue the I10 instruction using the guest's domain, and also supports the above-mentioned I10 instruction by controlling the value of the interrupt queue selection information. The purpose of the present invention is to provide a virtual machine control method that can notify the host of 110 interrupts.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. The virtual machine control method of the present invention includes a host hardware interrupt queue 41 provided corresponding to the host, a guest hardware interrupt queue 42 provided corresponding to the guest,
A physical subchannel 52 having a domain identifier and interrupt queue selection information, an input/output processor 4 that performs input/output processing and distributes input/output interrupts to the host or guest, and a channel 5. There is.

The host connects physical subchannels 52 . You can change the interrupt queue selection information within...

When the input/output processor 4 is notified of the end of input/output processing from the channel 5, it checks the interrupt queue selection information of the corresponding physical subchannel, and if the content of the interrupt queue selection information of the physical subchannel is a predetermined value, connects the physical subchannel to the host's hardware interrupt queue, and if the content of the interrupt queue selection information of the physical subchannel is not a predetermined value, connects the physical subchannel to the hardware interrupt queue of the guest specified by the domain identifier of the physical subchannel. Performs processing to connect the physical subchannel to the interrupt queue.

〔Example〕

FIG. 2 is a diagram illustrating interrupt management in the computer system of the present invention. In the figure, 72 indicates interrupt queue selection information. Note that the same reference numerals as in FIG. 4 indicate the same parts.

As shown in FIG. 2, in the present invention, interrupt queue selection information 72 is provided in the physical subchannel of the guest. The Hotos CPU 1 can change the value of interrupt queue selection information. If the interrupt queue selection information is 1, the interrupt request for the subchannel is reported to the host, and if it is 0, the interrupt request for the subchannel is reported to the host, and if it is 0, the interrupt request is reported to the host specified by the domain identifier that exists in the physical subchannel to which the interrupt queue selection information belongs. In the illustrated example, the domain identifier of the physical subchannel 52 specifies domain B, so when the interrupt queue selection information is O,
An interrupt request for the physical subchannel 52 is made by the guest CP.
Reported to U12.

If the I10 supervisor of the guest P2 is not installed, the host PI sets the value of the interrupt queue selection information 72 of the physical subchannel 52 assigned to the guest P2 to 1. Also, there is no interruption from guest P2! The process of writing a value to the 0 interrupt queue selection information that sets the value of the interrupt queue selection information 72 of the physical subchannel 52 to 1 even when a 10 instruction (channel reset instruction, etc.) is issued is as follows.
This is done using predetermined instructions. After performing such processing, the host P1 issues a command to start the guest I10.

When a 110 interrupt occurs, the I10 processor 4 interrupts the 110 interrupt.
In the interrupt generation routine, interrupt queue selection information 7
Check whether the value of 2 is 1.

When the value of the interrupt queue selection information 72 is 1, an interrupt is generated to the host P1 regardless of the contents of the domain identifier 62.

FIG. 3 is a diagram showing I10 activation→I10 processing→interrupt report in the present invention. In addition, Fig. 2.

The same reference numerals as in FIG. 5 indicate the same parts.

■ Host CPU 1 specifies the domain identifier for I10 instruction emulation and the I1 to be emulated.
0 command, subchannel number and control information 102 (C
A guest I10 instruction is issued using the storage address (CW address, etc.) as an operand. The content of the control information is reflected in the physical subchannel 52 by hardware or software for subsequent <110 operations.

(2) Channel 5 performs I10 processing with data space 302 according to channel control word 202 using physical subchannel 52.

(2) Channel 5 notifies the end of I10 processing by interrupt. (1) The processor 4 looks at the interrupt queue selection information 72 written in the physical subchannel 52, and if the content is 1, connects the physical subchannel 52 to the interrupt queue 41 for the host. If the corresponding bit of hardware interrupt mask 3O is open, the CPU
If an interrupt occurs at 1l and the bit is closed, the interrupt is bent. On the other hand, if the content of the interrupt queue selection information 72 is 0, the physical subchannel 52 is assigned to the interrupt queue 4 according to the content of the domain identifier 62.
Connect to 2.

■ By starting a new TEST I10 instruction (guest I10 instruction that does not involve an interrupt), the host CPU II issues an interrupt corresponding to the interrupt reported in ■ from the physical subchannel 52 connected to the hardware interrupt queue 41. Extracts information and performs corresponding interrupt processing.

With the above control, the control information 102. Channel control word 2
02. Even though all the data 302 exists in the guest space (domain B), it is possible to control not to report interrupts to the guest.

〔Effect of the invention〕

As is clear from the above explanation, 1. According to the present invention, the host can issue the ■10 instruction using the guest's domain without generating an I10 interrupt to the guest. I10 processing services can be performed flexibly.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a diagram explaining interrupt management in a computer system according to the present invention, FIG. 3 is a diagram showing I10 startup → ■10 processing → interrupt processing in the present invention, and FIG. The figure is a diagram explaining interrupt management in a computer system according to the conventional method, FIG. 5 is a diagram showing I10 startup → I10 processing → interrupt processing in the conventional method, and FIG.
The figure shows the configuration of the virtual computer system, and FIG. 7 shows the flow of processing when a system operation command is issued. l...Host space, 2...Guest space 1, 4...
I10 processor, 5...channel, 6...memory control device, 7...main storage device, 11...host) CP
U, 12...Guest CPU, 30-32...Hardware interrupt mask, 41 and 42...Interrupt queue, 51-53...Physical subchannel, 61-63...Domain identifier, 72... . . . Interrupt queue selection information, 101 . . . Control information, 201 . . . Channel control word, 301 . . . Data.

Claims (1)

[Claims] A host hardware interrupt queue (41) provided corresponding to the host, a guest hardware interrupt queue (42) provided corresponding to the guest, a domain identifier and an interrupt. The host is equipped with physical subchannels (52,...) having queue selection information, an input/output processor (4) that performs input/output processing and distributes input/output interrupts to the host or guest, and a channel (5). , is configured to be able to change the interrupt queue selection information in the physical subchannels (52,...), and when the input/output processor (4) is notified of the end of input/output processing from the channel (5), the input/output processor (4) responds accordingly. Check the interrupt queue selection information of the physical subchannel to be processed, and if the content of the interrupt queue selection information of the physical subchannel is a predetermined value, connect the physical subchannel to the hardware interrupt queue (41) of the host, and If the content of the interrupt queue selection information of the physical subchannel is not a predetermined value, a process is performed to connect the physical subchannel to the hardware interrupt queue (42) of the guest specified by the domain identifier of the physical subchannel. A virtual computer control method characterized by: