JPH03100975A - Modulator / demodulator - Google Patents

Abstract

PURPOSE:To lower the oscillation frequency of a VFO circuit without lowering transfer velocity and to improve stability by dividing the parallel conversion of write data and read data into even-numbered bits and odd-numbered bits and parallelly executing bit shift. CONSTITUTION:At the time of write access, a parallel converting means 100 loads write data, which are inputted for the unit of a byte, while dividing the data into the even-numbered bits and odd-numbered bits and afterwards, accord ing to a system clock CLK 2, the bit shift is executed and the 2 bit write data are parallelly outputted to a coding means 16. On the other hand, at the time of read access, the 2 bit read data to be parallelly outputted from a decoding means 18 are loaded while being divided into the even-numbered bits and odd- numbered bits according to the clock CLK 2 and afterwards, the bit shift is repeated. Then, the data are converted to the parallel bit data for the unit of the byte. Accordingly, the clocks to be used are a clock CLK 1 from a VFO circuit 20 and the clock CLK 2 from a frequency divider 22.

Description

[Detailed Description of the Invention] [Summary] A modulation/demodulation device that modulates write data to be modulated and recorded on a rotating recording medium from 2 bits to 3 bits, and demodulates code read data received in 3 bits to the original 2 bit read data. In order to lower the oscillation frequency of the VFO used for bit conversion without reducing the access transfer speed, we have developed a code that converts write data cut out in 2-bit units into a 3-bit write code according to the 1/7 code matching rule. It has a table and a decoding table that converts the code read data received in 3 bits into 2 bit read data according to the 1/7 code decoding rule, and performs bit shifting of the code data using the system clock directly oscillated by the 720 circuit. By lowering the VFO oscillation frequency and dividing the parallel conversion of write data and read data into even bits and odd bits and shifting the bits in parallel, the bit shift can be operated with a clock divided by 173 of the VFO oscillation clock. do.

[Industrial Application Field] The present invention modulates write data recorded on a rotating recording medium such as a disk into a 1/7 code, and demodulates 1/7 code read data from the rotating recording medium to the original data. The present invention relates to a modulation/demodulation device.

For write access of magnetic disk devices used as data recording devices, write data is transferred to MFM.
The data is modulated according to the method and written on the magnetic disk. Furthermore, in order to increase the recording density, modulation devices have recently been used that convert write data into a variable length constant ratio code and then modulate and write the code.

This variable length constant ratio code has a 2/7 (two-by-8) code that expands 1 bit of write data to 2 bits.
1/7 (one-b7-seye) Expands 2 bits of code and write data to 3 bits
n) cord, and 1/8 (one-b7 eig
ht) code, etc., but in recent years, 1/7 code, which expands 2 bits to 3 bits, has become mainstream.

On the other hand, when code data recorded on a magnetic disk by, for example, 1/7 code conversion is read out by a read access, 3-bit code read data is converted to 2-bit read data according to the 1/7 code decoding rule. The data is decoded and, for example, at the timing when the number of decoded read pits for one byte is obtained, it is captured and transferred to the host device.

By the way, high-speed data transfer is always required in magnetic disk devices and the like. In order to achieve this high-speed transfer, it is sufficient to simply increase the transfer rate, that is, the frequency of the system clock that determines bit writing and bit reading of data.

Usually, a variable frequency oscillation circuit (VFO circuit) is used to generate a system clock, and the system clock is created by dividing the frequency of the oscillation clock of the VFO circuit. Therefore, when the frequency of the system clock is increased, the oscillation frequency of the VFO circuit increases by the reciprocal of the frequency division ratio. V
The higher the oscillation frequency of an FO circuit, the more expensive high-speed circuit elements are required, the more complex the circuitry to ensure the stability of high-speed operation, and the higher the power consumption itself.
The burden on the device required for the vFO circuit becomes considerably large. Furthermore, as the system clock speeds up, it is necessary to use high-speed circuit elements in the logic circuits constituting the modulation circuit, which similarly causes the problem of increased current consumption and cost.

Therefore, it is desired to realize high-speed transfer by increasing the speed of the system clock without increasing the oscillation frequency of the VFO circuit.

[Prior Art] FIG. 9 is a block diagram of a conventional modulation/demodulation device, in which write data is cut out in units of 2 bits and modulated into 1/7 code of 3 bits, and 1/7 code is cut out in units of 3 bits. This figure shows a device that demodulates 2-bit read data from .

In FIG. 9, a VFO circuit 16 receives fixed data or a servo clock from the disk and oscillates a reference system clock of a stable frequency, for example, a reference system clock of 108 MHz. The reference system clock from the VFO circuit 16 is 36MH by the 1/3 frequency divider 26.
The frequency is divided into the system clock of z, and the frequency is divided into 1/2 frequency divider
The frequency is divided by 4 into a 54MHz system clock.

28 is a shift register, which loads the write data in byte units and outputs it serially during write access, and load-shifts the serial output of demodulated read data during read access to obtain parallel bit output for 1 byte. When the data is transferred to the host device, the data is transferred to the host device.

Reference numeral 30 denotes a two-stage shift register, which cuts out write data into 2-bit units during write access and converts the parallel output of demodulated 2-bit data into serial data during read access.

32 is an encoder/decoder, which includes a 1/7 code code table that converts 2-bit data into 3-bit code data, and 1 that converts 3-bit code into 2-bit data.
/7 code decoding table. Reference numeral 34 denotes a three-stage shift register, which serially converts a modulated 3-bit code during write access, and extracts 3 bits of code read data during read access.

Furthermore, 36 is an AND gate that generates a parallel load signal, and enables the parallel load signal for the shift register 30 during write access in synchronization with the rise of each system clock of the 172 frequency divider 24 and the 1/3 frequency divider 26. Modulate the 2-bit data into a 3-bit code as
At the time of write access, the parallel load signal to the shift register 34 is enabled and 2-bit data is demodulated from 3-bit code data.

FIG. 10 shows the reference system clock of FIG. 9, 1/3.
It is a timing chart of a system clock (divided clock) whose frequency is divided by 1/2.

First, to explain the operation during write access, for example, at time 11, a parallel load signal that goes to H level is obtained from the AND gate 36, and the 2-bit write data of the shift register 30 is transferred to the encoder/decoder 32 whose encoder function is enabled. The code is loaded into the shift register 34 after being converted into a 3-bit 1/7 code.

Also, the rising time of the 1/2 frequency divided clock 54MHz,
The 3-bit code loaded into the shift register 34 at each time t2.14 undergoes a bit shift and is serially converted into code write data. At the same time, the 1/3 frequency divided clock 36MHz rises 11. At t3, the next 2-bit write data is loaded into the shift register 30. Then, at time [5], which is the sixth period of the reference system clock from time t1, 273-bit conversion is performed in the same manner as time t1, and this is repeated thereafter.

Next, to explain read access, at time t1, the parallel load signal that goes to H level from the AND gate 36 becomes valid for the shift register 34, and the shift register 34
The 3-bit code read data is loaded into the encoder/decoder 32 whose decoding function is enabled.
After converting to bit read data, shift register 30
Load in parallel.

On the other hand, the rising time 1 of the 1/2 frequency divided clock 54MHz
1. At each time t2.14, the next 3 bits of code read data are loaded and shifted to the shift register 34, and at time t5, the AND gate 36 is loaded and shifted again.
The decoding process is performed by obtaining the parallel load signal. At the same time, the shift register 3 is decoded at time t1.
The 2-bit read data loaded in parallel to 0 becomes 1
At the rising edge of the 36 MHz divided clock from the /3 frequency divider 24, the bit shift is performed at 13, and the data is loaded and shifted into the shift register 28 through serial conversion, and the next decoded 2-bit read is performed at time 15. The parallel load of data is shifted.

Repeat this below. The register 28 receives data for upper transfer at the timing when the parallel output of one byte worth of read data bits is obtained.

[Problems to be Solved by the Invention] However, in such a conventional modulation/demodulation device, at the time of write access, the 2-bit extraction of write data and the serial conversion output after conversion to a 3-bit code are synchronized. In addition, during read access, in order to synchronize the 3-bit code extraction with the serial conversion output after 2-bit conversion, the frequency ratio of the system clocks for both is set to 2:3 (on the contrary, the period is 3:2). 2
The various system clocks are obtained by frequency-dividing the oscillation clock of the VFO circuit.

Therefore, the oscillation frequency of the VFO circuit is 108 MHz, which is the least common multiple of the 2-bit extracted clock frequency of 36 MHz and the 3-bit serial conversion clock frequency of 54 MHz.
Must be set at z.

If the oscillation frequency of the VFO circuit is high in this way, high-speed circuit elements that are more expensive than other circuit parts must be used in the VFO circuit, and the compensation circuit for improving stability becomes complicated. Furthermore, there was a problem of high power consumption.

The present invention has been made in view of these conventional problems, and an object of the present invention is to provide a modulation/demodulation device that can lower the oscillation frequency of the VFO circuit without reducing the transfer speed, thereby improving stability and reducing costs. shall be.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

First, the present invention is directed to a modulation/demodulation device that modulates and demodulates a variable length constant ratio code with a rotating recording medium such as a magnetic disk or an optical disk.

In the present invention, for such a modulation/demodulation device, there is provided system clock generation means 10 for generating a system clock of a predetermined frequency in synchronization with an external signal;
a coding means 16 for cutting out the food read data read from the rotating recording medium into 3-bit units and converting it into a 3-bit code according to a predetermined matching rule, and then serially transferring and writing it to the rotating recording medium; a decoding means 18 for converting into 2-bit read data according to decoding rules and outputting it in parallel; at the time of write access, the write data input in bytes is divided into even bits and odd bits, loaded, and then bit-shifted according to the system clock; from the last shift stage to the matching means 16.
On the other hand, during read access, the 2-bit read data output in parallel from the decoding means 18 is divided into even bits and odd bits, loaded according to the system clock, and then bit shifted repeatedly to be processed in byte units. A parallel conversion means 100 for converting into parallel bit data is provided.

Here, the parallel conversion means 100 has an even number bit shift means 20 and an odd number bit shift means 22. At the time of write access, the even number bits of the write data input in byte units are loaded into the even number bit shift means 20, and at the same time After the bits are loaded into the odd bit shifting means 22, they are shifted in parallel according to the system clock, and two sets of 2-bit write data are sent to the encoding means 16 in parallel for each bit shift from the last shift stage and the second to last shift stage. Output.

Further, during read access, every time 2-bit read data is output in parallel from the decoding means 18, even number bits are shifted to the even number bit shift means 12 according to the system clock.
At the same time, the odd bits are loaded into the first stage of the odd bit shifting means, and the already loaded bits are shifted respectively, at the timing of loading and bit shifting a predetermined number of times by the even bit and odd bit shifting means 12 and 14. The obtained parallel bit data in units of bytes is taken in as transfer data to the host device.

Here, the system clock generating means 10 includes a variable frequency oscillator 20 that receives read data or servo data, oscillates a reference system clock of a predetermined frequency, and supplies it to each of the encoding means 16 and the decoding means 18 as a code data shift clock CLKI. and: A system clock is created by dividing the period of 1 into 1/3 of the reference system clock CL from the variable frequency oscillator 20, and the parallel conversion means 1
00 as a bit shift clock CLK2.

Further, the encoding means 16 converts the write data cut out into 2-bit units, for example, into a 3-bit code based on the last bit of the previously converted 3-bit data and the 2-bit write data to be converted next. /7 code conversion table etc.

The decoding means 18 converts code read data cut out into 3-bit units, for example, into 2-bit read data based on the previous and next 3-bit read data.
/7 code decoding daple etc.

Furthermore, encoding means 1 equipped with a 1/7 code conversion table
6 converts the last 2-bit write data input in bytes into 3-bit code write data,
Since 2-bit write data from the beginning of the byte-based write data to be loaded next is required, each of the even-numbered bit shift means 12 and the odd-numbered bit shift means 14 shifts from the second to last shift stage on a byte-by-byte basis. At the same time, the first odd bit and even bit of the byte-by-byte write data to be processed next are directly loaded into the second to last shift stage and encoded. It is configured to output to means 16.

[Function] In the modulation/demodulation device of the present invention having such a configuration, the oscillation frequency of the VFO circuit is a frequency that matches the system clock for serial or parallel conversion of 3-bit code data after modulation and before demodulation. On the other hand, the system clock used for parallel or serial conversion of 2-bit data before modulation and after demodulation should be a system clock obtained by dividing the reference system clock oscillated by the vFO circuit into 1/3. Bye.

Therefore, a system clock that uses the oscillation frequency of the VFO circuit for parallel/serial conversion of 2-bit data,
There is no need to set a high frequency that is the least common multiple of the system clock frequencies used for parallel/serial conversion of 3-bit codes, and there is no need to change the transfer speed (VF
The oscillation frequency of the O circuit can be reduced to 1/2 of the conventional one.

That is, the frequency of the system clock used for bit conversion of 1/7 code scaled data after modulation or before demodulation is
As in the conventional case, if the frequency is 54 MHz, the VFO circuit may directly oscillate the system clock CL) [1 with a frequency of 54 MHz as the reference system clock. The system clock used for bit conversion of write data before modulation or after demodulation is the 18MHz system clock CK, which is the standard system clock from the VFO circuit divided by 1/3.
You can use L2.

Therefore, lowering the oscillation frequency of the VFO circuit reduces circuit cost and improves stability, and the system clock for bit shifting for parallel conversion can also be made sufficiently low, making it a low-speed circuit element that is inexpensive in list price. It also provides high stability and can significantly reduce costs.

[Embodiment] FIG. 2 is a block diagram showing an embodiment of the present invention.

In FIG. 2, 10 is a system clock generation circuit, which includes a vFO circuit (variable frequency oscillation circuit) 20 and 173.
A frequency divider 22 is provided. The VFO circuit 20 oscillates a reference system clock of a predetermined frequency based on external read data or a servo clock, and directly supplies it as a code data shift clock CLKI to the modulation/demodulation section 200, which will be explained later. are doing. Here V
The oscillation frequency of the FO circuit 20 is set to 54 MHz, for example.

The 1/3' frequency divider 22 outputs the oscillated 5 of the VFO circuit 20.
A system clock is generated by dividing the 4 MHz reference system clock into 1/3, and is supplied as a 2-bit data shift clock CLK2 to the parallel conversion circuit section 100, which will be explained later, to adjust the oscillation frequency of the VFO circuit 20. 18MHz because 54MHz is divided into 1/3
This is the system clock for z.

The modulation/demodulation section 200 is provided with a code table 16 and a decoding table 18. The code table 16 stores conversion table information according to the 1/7 code conversion rule, and the decoding table 18 stores table information according to the 1/7 code decoding rule.

Specifically, the code table 16 stores table data according to the code table shown below.

Code table However, 00 means not 00, and X is a bit care.

That is, in the code table 16, according to the code table, the 2-bit byte data as the current data is reduced to 1/7.
This is to convert into 3-bit code data that has been subjected to food conversion, and this code conversion requires 2 bits of the write data that will be converted next. Therefore, code table 16
, the parallel converter 100 provided at the previous stage outputs 2 bits of write data b00. as current data.
bQl and the next 2-bit write data b02. b
03 are input in parallel.

On the other hand, the decoding table 18 stores table information according to the 1/7 code decoding table shown in the following table.

Decoding Table However, 00 means not 00, and X is a bit care.

That is, the decoding table 18 receives the 3-bit parallel input of code read data read from the magnetic disk side as current data, and converts this 3-bit code read data into the original 2-bit data. As is clear from the decoding table, this 3-bit code decoding conversion requires the previous 3-bit code read data and the next 3-bit code read data.

Regarding the code rules and decoding rules for realizing the code table 16 and decoding table 18, Japanese Patent Laid-Open No. 58-1
19273 in detail.

The modulation/demodulation section 200 further includes a three-stage shift register 3.
8 is provided. During a write operation, the shift register 38 loads the 3-bit code write data CO, CI, and C2 output in parallel from the code table 16, and then receives a bit shift based on the code data shift clock from the VFO circuit 20. Convert it to serial data and output it to the disk as serial code write data. Also, during read operation, the serial code read data obtained from the disk side is sent to the VF.
Code data shift clock CLKI from O circuit 20
After sequentially loading bit by bit, the bits are shifted, and 3-bit parallel code read data Co, C1,
It is outputted as C2 to the decoding table 18, and outputted in parallel as 2-bit write data RBO, RBI according to the decoding table.

Parallel converter 10 provided upstream of modulator/demodulator 200
0 is provided with an even number bit shift circuit 12 and an odd number bit shift circuit 14.

Even number bit shift circuit 12 and odd number bit shift circuit 1
4 is a data buffer 40.42 during a write operation.
The 2-byte write data bits stored in bytes are divided into even bits and odd bits and loaded into each of them, and after loading, they are parallelized by the 2-bit data shift clock CLK2 from the 1/3 frequency divider 22. bit-shifted. This parallel bit shift during write operation is performed by cutting out the write data into 2-bit units and using the code table 1.
Specifically, the output b00.6 of the final shift stage in the even bit shift circuit 12 and the odd bit shift circuit 14. bol and the outputs b02 and b03 of the second to last shift stage are provided to the code table 16. Therefore, in the loading state divided into even bits and odd bits, the first 4 bits of 2-byte write data are output in parallel to the code table 16, and the first 3 bits can be converted into code write data according to the code table. .

Next, in response to the 2-bit data shift clock CLK2, the
When the second bit shift is performed, the code table 16
4 bits from the 3rd to 6th of the 2-byte data are output in parallel, and the next 3rd and 4th bits are output in parallel.
Bit write data is converted into a 3-bit code. Thereafter, bit shifting is performed in the same way up to the last two bits of the two-byte data, but since the next two bits of write data do not exist in the byte data for the last two bits, at this time the data buffer 40 .4
The first two bits of the next two bytes of write data prepared on the second side are output as bits 02.03 of the code table, and the last two bits of the two bytes of data currently being processed are converted into a 3-bit code. has been realized.

Processing during a write operation by the parallel converter 100 will be further explained in the following description.

Next, in the parallel conversion unit 100 during the read operation, since the 2-bit read data RBO, RBI decoded from the decoding table 18 is obtained as a parallel output, the even number bit RBo is transferred to the even number bit shift circuit 12.
At the same time, the bit data that has already been loaded is bit-shifted, and the odd-numbered bit RBI is loaded into the first stage of the odd-numbered bit shift circuit 14, and at the same time, the already loaded bits are bit-shifted. Then, at the timing when four 2-bit write data are obtained from the decoding table 18, the even bit shift circuit 12 and the odd bit shift circuit 14 each generate a 4-bit parallel output, so this is transferred to the data buffer 40. The data is read as 8-bit 1-byte read data for transfer to the host device. When one byte worth of read data is obtained in this way, for the next one byte, the load shift is repeated for the remaining four unused shift stages in the even bit shift circuits 12 and 14, and the load shift is repeated four times. At the timing when the 2-bit write data is obtained, the next byte read data of 1 byte, which is 8 bits, is taken into the data buffer 42 side for transfer to the higher-level device.

Parallel converter 100 during such a read operation
The operation will also be further clarified in the following description.

Next, comparing the system clock frequency of the embodiment shown in FIG. 2 with that of the conventional device shown in FIG. Regarding the data shift clock CLK1, that is, the reference system clock directly oscillated by the VFO circuit 20, the frequency of the present invention is 54 MHz, which is half of the conventional IQ8 MHz.
Since it is possible to use low-speed circuit elements, it is possible to reduce costs and guarantee operational stability at the same time. Also, 2 bits for the parallel converter 100 used for extracting 2 bits of write data and converting byte data of decoded data.
The bit data shift clock CLK2 is the conventional 36
By lowering the clock frequency to 18 MHz, which is half of the MHz, even slower circuit elements can be used as the circuit elements constituting the parallel conversion circuit section 100, making it possible to reduce the cost and power consumption.

FIG. 3 is a block diagram of an embodiment of the even bit shift circuit 12 provided in the parallel converter 100 of FIG. 2, and the odd bit shift circuit 14 is shown in FIG. Note that this embodiment deals with byte data having an 8-bit configuration.

The even bit shift circuit 12 in FIG. 3 includes eight FFs 50-0.50-2.50-0.50-2, which constitute a shift stage, for the eight even bits of 2-byte data. ...φ50-14 is provided.

FF50-8.50-10.50-12.50- outputting upper shift data bits 08.10, 12°14
14 is supplied with a 2-bit shift clock A, while the lower shift data bits 00.02, 04,
FF50-0.50-2.50-4.5 outputting 06
A 2-bit data shift clock B is supplied to 0-6. 2-bit data shift clocks A and B supply the same 2-bit data shift clock CLK2 shown in FIG. After A is supplied for four cycles, the supply of the 2-bit data shift clock B is switched and similarly supplied for four cycles, and this is alternately repeated.

FF50-0 configuring eight shift stages. ...5
0-14 is preceded by an OR gate 52-0. 52-2.
...52-14 are provided. The OR gates 52-2 and 52-6 are three-man powered OR gates, but all the others are two-man powered OR gates.

OR gate 52-0. ...1 of the inputs of 52-14
One is AN for loading bit data from outside.
D gate 54-0.54-2.・φ・54-14 is provided. Konchi, AND gate 54-0.54-2.
...The parallel load A signal is commonly input to one side of 54-14, and the 8 even bits 00 in the 2-byte write data obtained from the previous stage buffer
．． 02. ...14 are input.

AND gate 56-0.56-2. ...56-1
2 is used to shift bits from the previous shift stage to the next shift stage, and upper shift data 08, 10, 1
Three shift AND gates 56- compatible with 2.14
A shift A signal is applied to 8.56-10.56-12, a shift C signal is applied to a shift AND gate 56-6 provided between shift data bits 06 and 08, and a shift C signal is applied to Bit 00.02.04゜0
A of the three AND gates provided corresponding to 6
ND game) 56-0. - A shift B signal is applied to 56-4, and a shift D signal is input to AND game 56-2.

The shift C signal for the AND game 56-6 is used to divide the shift stage into upper bits and lower bits during a read operation, and the same signal as the shift A signal is applied during a write operation.

In addition, the shift D signal is used to separate shift data bits 02 and 04 when outputting the last 2 bits of 2 bytes loaded in parallel during a write operation. It is the same signal as the B signal, and the shift B signal becomes the same signal as the shift A signal during a write operation.

Furthermore, the remaining inputs of the three-man OR gate 52-2 include A.
An ND gate 60-2 is provided. AND gate 60-
The parallel load signal B is inputted to one of the gates 2 and 2, and the parallel load signal B becomes H level at a timing one before the bit shift of the last 1 bit of the 2-byte data, putting the AND gate 60-2 in an allowable state. , At this time, OR gate 52-
2 to the FF 50-2.

Furthermore, an AND gate 58-6 provided at the input of the OR gate 52-6 and an AND gate 58-14 provided at the input of the OR gate 52-14 read parallel read data from the decoding table 18 provided in the modulation/demodulation section. even bit 0 of
(RBO) is input, AND game 158-14 is set to the allowable state by the read shift A signal, and
The gate 58-6 is placed in an allowable state by the read shift B signal. That is, during a read operation, the read shift A signal goes high while the parallel read data bits O for four times are obtained, and bit loading to FF5O-14 is performed four times, and then the read shift B signal goes high. By setting the AND gate 58-6 to the allowable state, the parallel read data bit 0 for the next four times is transferred to the FF50-6.
The bit load will be set to 6.

The circuit configuration itself of the odd bit shift circuit 14 in FIG. 4 is exactly the same as the even bit shift circuit in FIG. 3, and the signal relationships for bit loading and bit shifting are also the same, and parallel loading is performed during write operation. The only difference is that bit data or bit data that is serially loaded during a write operation is an odd number of bits.

Next, the write operation (write access) of the present invention using the even and odd bit shift circuits of FIG. 3.4 will be explained with reference to the timing chart of FIG.

Now, at the timing of time t1 in FIG.
The write data stored in 0.42 is (9222)H in hexadecimal as shown in FIG.
The write data bit number indicated by 15 is divided into even bits and odd bits.

System clock C from 1/3 frequency divider 22 at time tl
When the 2-bit data shift clocks A and B that match LK2 rise, the parallel load A signal is turned on from the previous time tO and the bit load is possible, so the 2-byte write is performed as shown in Figure 6. Even bits of data are loaded into even bit shift circuit 12 and odd bits are loaded into odd bit shift circuit 14. Therefore, in the load state immediately after time t1, the shifted data bit outputs of the even bit and odd bit shift circuits 12 and 14 are binary data as shown. Immediately after such loading at time t1, shift data bit 00.02 of the even bit shift circuit 12 and shift data bit 01.03 of the odd bit shift circuit 14 are respectively output in parallel to the code table 16 of the modulation/demodulation section 200. Therefore, at this time, the current data in the code table is "10" and the next data is "01". Therefore, for example, if the previous waiting bit data was 0, the 3-bit code becomes "101". The converted output is obtained.

The 3-bit code read data obtained from the code table 16 is loaded into the shift register 38, and then the 2-bit data shift clock A is loaded.

At the rising edge of the three code data shift clocks up to time t2 when B rises, the data is bit shifted and converted into parallel code write data, which is written to the magnetic disk.

Thereafter, the bit shifts of the even number bit shift circuit 12 and the odd number bit shift circuit 14 by the 2-bit data shift clocks A and B are repeated at each of times t2 to t8, and at the final timing of time t8, the 2 bytes loaded at time tl are repeated. The last two bits of data are in a parallel output state.

However, in the bit shift at time t8, even if the last 2-bit write data loaded in bytes is output in parallel, the next 2-bit write data necessary for conversion according to the code table does not exist.

Therefore, at time t7, one time before time t8, the parallel load B signal is set to H level, and the AND gates 60-2 and 60-3 corresponding to shift data bits 02 and 03 in FIGS. 3 and 4 are turned on. , At this time, input the first even bit and the next odd bit of the next two bytes of write data already stored in the data buffer 40.42, and at time t8 input the last two bits for FF50-0.50-1. At the same time as each bit of data is shifted, the first two bits of the next byte data are loaded, and the last two bits of write data are added to the code table 16 as current data.
The first 2-bit data of the next byte is output in parallel as the next data and converted into a 3-bit code.

Here, the storage of the next 2-byte data into the data buffer 40.42 has already been completed between times t3 and t4, and the data buffer 40.42 has 16 bytes stored in the data buffer 40.42.
Write data of (88CB)H in decimal is stored. Data storage in the data buffers 40 and 42 is performed using tl
<(Storage)> Anywhere is fine as long as t8 is satisfied.

At time t8, the conversion of the last 2-bit write data into a 3-bit code is completed, and the parallel load A signal goes high.
level, parallel bit loading of 2-byte write data (88CB) H is performed at the next time t9, and conversion into a 3-bit code by 2-bit extraction is repeated in the same manner.

The parallel output of the last two bits of the write data at time t8 is the same for time to when the bit shift of the parallel load data before time tl is finally performed, and the parallel output at the timing one before time to The H level of the load B signal causes the process to load 2-byte data (92222) H to be processed next.

Next, the read operation according to the present invention will be explained with reference to the demodulation timing chart of FIG.

In the demodulation timing chart of FIG. 7, from the decoding table 18, the 2-bit parallel read data bit 0.1 is decoded from the 3-bit code in synchronization with the rising timing of the 2-bit data shift clocks A and B.
(RBO, RB1) is sequential, even bit shift circuit 1
2 and odd bit shift circuit 14, respectively.

Here, in the demodulation timing chart of FIG. 7, the operation will be described in a state where 2 bytes of decoded read data from time t1 to t8 are obtained.

First, at time tl-yt4, the 2-bit data shift clock A becomes valid, and the read shift A signal and shift signal A become H level at the timing of time to, which is one time before time tl, and vice versa. The shift B signal, shift B and D signals are at L level.

Therefore, for example, the bit load and shift functions of the circuit section corresponding to the upper shift data bits 08.10.degree. 12.14 of the even-numbered bit shift circuit 12 in FIG. 3 become effective. Note that the shift C signal is always at L level, and the A
By turning off the ND game) 56-6, the upper and lower shift data bit groups are separated.

This also applies to the odd bit shift circuit 14 shown in FIG.

When the 2-bit data shift clock A rises at time t1, the values of parallel read data bits 0 and 1 at that time are shifted to the first stage of even bit shift circuit 12 and odd bit shift circuit 14, that is, shift data bits 14.1.
Bitloaded to 5. At the next time t2, each value of the newly obtained parallel read data bit 0.1 is bit-loaded into each of the shift data bits 14.15, and at the same time, the bit data bit-loaded at time tl is transferred to the next stage. Bit shifted to shift data bits 12 and 13.

Similarly, time t3. Bit loading and bit shifting are performed at timing t4, and even bit shift circuit 12 and odd bit shift circuit 1 are switched at time t4.
One byte worth of read data, which is 8 bits, is obtained as a parallel output of the upper four shift data bits of 4.

At time t4, the read shift A signal and shift A signal, which had been at H level, fall to L level.
Also, the read shift B signal and shift B and D signals, which had been at L level, rise to H level, and the third and fourth signals
Lower shift data bits 00,
The circuit sections corresponding to 02.04°06, 01, 03.05, and 07 are valid.

Subsequently, from time t5, 2-bit data shift clock B becomes effective in place of the previous 2-bit data shift clock A, and decoding table 1 obtained at time t5
Parallel read data bits 0 and 1 from 8 are transferred to the 3rd and
The first lower FF 50-6, 50-7 in the even bit shift circuit 12 and the odd bit shift circuit 14 in FIG.
to produce shift data bits 06 and 07.

After time t5, the upper four bits of the even bit shift circuit 12 and the odd bit shift circuit 14 have already been transferred at time t4.
Since one byte of parallel read data has been obtained from the parallel output of the bits, the upper byte is taken into the data buffer 40 at this point. This acquisition may be performed anywhere as long as t4<(intake)<t9.

Similarly, time t6. t7. Bit loading and bit shifting are performed in synchronization with the rising edge of the 2-bit data shift clock B at time t8, and the data of the lower byte is read at the timing one after the next 1 byte of parallel read data is generated at time t8. The data is taken into the buffer 42, and this process is repeated thereafter.

FIG. 8 is the demodulation timing chart of FIG. 7, and shows a byte-by-byte collection of shifted data bits obtained by parallel bit loading of 2 bytes from time tl to t8 to the even bit shift circuit 12 and the odd bit shift circuit 14. First, the upper 4 bits of the even bit shift circuit 12 and the odd bit shift circuit 14 are obtained through the processing from time t1 to t4, so these are combined into one read byte data 00 (upper byte), Since the lower 4 bits of the even number bit shift circuit 12 and the odd number bit shift circuit 14 are obtained at the next time t5 to t8, these are collected as data 01 (lower byte).

In the above embodiment, the oscillation frequency of the VFO circuit 20 is set to 54.
MHz, that is, the code data shift clock CLKI for the modulation/demodulation section 200 is 54 MHz.

The 2-bit data shift clock CLK2 from the 1/3 frequency divider 22 to the parallel conversion circuit 100 is set to 18 MHz.
However, the frequency of these shift clocks can be set to an appropriate frequency as necessary.

Further, the modulation/demodulation section 200 in the above embodiment is 1/7
Although the code coding rules and decoding rules were taken as an example, the present invention is not limited to this. Write data is cut out in 2-bit units and converted into a 3-bit code, and the 3-bit code is converted into the original 2-bit code. Any suitable method can be adopted as long as it is a 1/7 code code and decoding to be decoded into bit data, for example, the 1/7 code modified from the 1/7 code
The present invention can be applied as is to the encoding rules and decoding rules shown in No. 51.

[Effects of the Invention] As explained above, according to the present invention, the oscillation frequency of the system clock oscillated by the VFO circuit can be changed without changing the transfer speed for write access and read access.
The cost can be reduced to half that of the conventional one, and the VFO circuit can be configured with low-speed circuit elements, which reduces costs, improves stability, and reduces current consumption.

At the same time, by parallel shift processing that separates the even bits and odd bits in the circuit section that performs parallel conversion for the modulation/demodulation section, it can be realized at half the clock frequency of the conventional one, and in this respect, it is also possible to use slower circuit elements. , it is possible to reduce costs, improve stability, and reduce current consumption.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention; Fig. 2 is a block diagram of an embodiment of the present invention; Fig. 3 is a block diagram of an embodiment of an even bit shift circuit of the present invention; Fig. 4 is a diagram of an odd bit shift circuit of the present invention. Fig. 5 is a modulation timing chart of the present invention; Fig. 6 is an explanatory diagram of distribution of 2-byte write data according to the invention; Fig. 7 is a demodulation timing chart of the invention; Fig. 8 is a diagram showing the distribution of 2-byte write data according to the invention; The byte distribution of parallel conversion data during demodulation is illustrated in an explanatory diagram; FIG. 9 is a configuration diagram of a conventional device; FIG. 10 is a timing chart of a conventional device. In the figure, 10 system clock generation means (circuit) 12: Even number bit shift means (circuit) 14: Odd number bit shift means (circuit) 16: Encoding means (code table) 18: Decoding means (decoding table) 20: Variable frequency Oscillation circuit (VFO circuit) 22: Frequency divider 38: Shift register 50-θ to 50-15: F F 52-0 to 52-15 + OR gate 54-0 to 54-15: A N D gate (for parallel bit load ) 56-0 to 56-13: A N D gate (for shift)
58-6.7.14.15: A N D gate (for loading serial bits) 6 [1-2, 60-3 A N D gate (for loading the first 2 bits of the next byte) 100; Parallel conversion means (conversion section) 200: Modulation/demodulation section

Claims (7)

[Claims] (1) System clock generation means (10) that generates a system clock of a predetermined frequency in synchronization with an external signal; Cuts out the write data into 2-bit units, converts it into a 3-bit code according to a predetermined coding rule, and then transfers it to a rotating recording medium. Coding means (16) for serially transferring and writing; and decoding means (18) for cutting out the code read data read from the rotating recording medium into 3-bit units, converting it into 2-bit read data according to a predetermined decoding rule, and outputting it. ); At the time of write access, the write data input in bytes is divided into even bits and odd bits and loaded, and then the bits are shifted according to the system clock and the 2-bit write data is transferred from the final shift stage to the encoding means (16). On the other hand, during read access, the 2-bit read data output in parallel from the decoding means (18) is divided into even bits and odd bits, and loading and shifting are sequentially repeated according to the system clock to obtain parallel bit data in bytes. A modulation/demodulation device comprising: a parallel conversion means (100) for converting into a parallel converter; (2) The parallel conversion means (100) has an even number bit shift means (12) and an odd number bit shift means (14), and at the time of write access, the even number bits of the write data input in bytes are shifted by the even number bits. means(
12) and at the same time, the odd bits are loaded into the odd bit shifting means (14), and then the bits are shifted in parallel according to the system clock. The set of 2-bit write data is encoded by the encoding means (16
2. The modulation/demodulation device according to claim 1, wherein the modulation/demodulation device outputs the signals in parallel to each other. (3) The parallel conversion means (100) has an even number bit shift means (12) and an odd number bit shift means (14), and during read access, 2-bit read data is output in parallel from the decoding means (18). Every time it is done,
In accordance with the system clock, even bits are loaded into the first stage of the even bit shifting means (12) and odd bits are simultaneously loaded into the first stage of the odd bit shifting means (14), and the already loaded bits are shifted respectively, and the odd bits are shifted. and even bit shift means (12, 14)
Claim 1 characterized in that parallel bit data in units of bytes obtained at the timing of loading and bit shifting a predetermined number of times is taken in as data to be transferred to a host device.
The modem described above. (4) The system clock generating means (10) receives read data or a servo clock, generates a reference system clock of a predetermined frequency, and supplies the code data shift clock to each of the decoding means (16) and the decoding means (18). Variable frequency oscillation circuit (2) supplied as (CLK1)
0); A system clock is created by dividing the reference system clock from the variable frequency oscillator (20) into 1/3, and a bit shift clock (
2. The modulation device according to claim 1, further comprising: a frequency divider (22) for supplying CLK2). (5) The encoding means (16) converts the write data extracted into 2-bit units into 3 bits based on the last bit of the previous converted 3-bit code data and the next converted 2-bit write data. 2. The modulation device according to claim 1, further comprising a 1/7 code matching table for converting into a code. (6) The decoding means (18) converts the code read data cut out into 3-bit units into 2-bit read data based on the previous 3-bit code data and the next 3-bit code data. 2. The modulation device according to claim 1, further comprising a /7 code decoding table. (7) Each of the even-numbered bit shifting means (12) and the odd-numbered bit shifting means (14) bit-shifts the final bit loaded in byte units to the second shift stage from the final stage, and at the same time, 2. The modulation device according to claim 1, further comprising means for loading each of the leading odd bits and even bits of the byte-by-byte write data to be processed next and outputting them to the encoding means (16).