JPH03101161A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a semiconductor integrated circuit that protects the gate of a CMOS type semiconductor circuit from dielectric breakdown.

B. Prior Art The gate of a CMOS semiconductor circuit is susceptible to dielectric breakdown due to surges such as static electricity, and must be protected by an input protection circuit. Figure 4 shows the configuration of a conventional semiconductor integrated circuit with an input protection circuit (RC
(Quoted from page 7 of “MoS IC Utilization Manual”)
. The semiconductor integrated circuit shown in FIG. 4 consists of a P-channel MO8FET (pMO8F
ET) 41 and n-channel MO8FET (nMO
3FET) 42, and an input protection circuit 43 connected to the input side of this CMOS inverter.

The input protection circuit 43 is pMO8FE'r41 or n
This is to prevent dielectric breakdown of the gate oxide film of MO8FET42, and the diode 44°45 and resistor 4
It consists of 6.

For example, when the voltage Vin of the input signal becomes higher than the power supply voltage vDD or lower than the potential of the power supply voltage Vss due to static electricity, a current flows through the diode 44 or the diode 45, and the CMOS connected to the subsequent stage
Inverter is protected.

FIG. 5 shows a cross-sectional structure of the input protection circuit 43 shown in FIG. 4 on a substrate.

A P3 diffusion region 51 is formed on the n-type semiconductor substrate 5o to constitute the resistor 46, and the p1 diffusion region 51 is pn-junctioned with the n-type semiconductor substrate 50 to constitute the distributed diode 44. An input signal Vin is guided to one end of the P+ diffusion region 51 via an aluminum wiring 52, and the other end is connected to an aluminum wiring 53. This aluminum wiring 53 is led to the gate of the CMOS inverter, but on the route, it is electrically connected to an n+ diffusion region 55 formed further inside a p-well region 54 provided in the n-type semiconductor substrate 50. ing. The P well region 54 is connected to a power supply terminal (not shown) having a power supply voltage VSS, and the n″″ diffusion region 55
A diode 45 is formed between the two. Furthermore, 59
is a silicon oxide film.

Further, as another example of a structure of a semiconductor integrated circuit having an input protection circuit, there is Japanese Patent Application Laid-Open No. 12158/1988 [Semiconductor Integrated Circuit]. This semiconductor integrated circuit uses an input protection circuit consisting of an inverter circuit using bipolar transistors, and has the advantage of realizing faster circuit operation as the integrated pattern becomes finer.

C3 Problems to be Solved by the Invention Incidentally, in the conventional semiconductor integrated circuit shown in FIG. 4, the voltage Vin of the input signal is applied to the gate of the CMOS inverter via the resistor 46 in the input protection circuit 43. Furthermore, there was a problem in that the resistance value of the resistor 46 could not be made sufficiently large in order to shorten the signal transmission delay time, resulting in insufficient input protection. For example, when a device housing is charged and a surge due to static electricity is applied as an input signal, a large current flows in an extremely short period of time, and the diodes 44 and 45 cannot sufficiently avoid overvoltage, causing the gate of the CMOS inverter to Destroys the oxide film.

Although the semiconductor integrated circuit disclosed in Japanese Unexamined Patent Publication No. 63-12158 solves this problem, the inverter circuit using bipolar transistors and transistors that constitute the input protection circuit is susceptible to malfunction due to noise. , there was a problem that the noise margin was small. For example, the pn junction forward voltage drop VF of a silicon device is approximately 0.6 at room temperature.
(V), which decreases to approximately 0.3 (V) at high temperatures. Therefore, if noise with a potential of 0.3 (V) or more is applied to the base of a bipolar transistor at high temperatures, malfunction will occur. Ru.

The present invention increases the noise margin when an input signal is supplied to an input stage CMOS type semiconductor circuit via an inverter circuit using bipolar transistors.

91 Means for Solving Problems The present invention will be explained in conjunction with FIG. 1 showing an embodiment.
The present invention is applied to a semiconductor integrated circuit having an OS type semiconductor circuit 10 and an input protection circuit 13 inserted between an input signal input terminal and the gate. The above problem is solved by inputting an input signal to the gate of the input stage CMOS type semiconductor circuit 10 via the emitter follower circuit 16.

The E0 action input signal is input to the gate 1 of the input stage CMOS type semiconductor circuit 10 via an emitter follower circuit 16 using a bipolar 1 transistor 14. Basically, the bipolar transistor 14 has a structure that is extremely resistant to electrostatic discharge damage, and the emitter follower circuit 16 using the bipolar 1 helangister 14 provides sufficient input protection.

In addition, the input signal is slightly converted in signal DC level by the emitter follower circuit 16 to the CMO3 semiconductor circuit 10.
CM that has a large noise margin because it is input into
The features of the OS type semiconductor circuit 10 can be utilized.

In the above-mentioned sections and section E, which describe the present invention in detail, figures of embodiments are used to make the present invention easier to understand, but the present invention is not limited to the embodiments.

F. Embodiment An embodiment of the present invention will be explained with reference to FIGS. 1 and 2. FIG.

FIG. 1 shows the configuration of the semiconductor integrated circuit. This semiconductor integrated circuit includes p-channel type MO8FET (PMO3FET) 11 and n
Channel type MO8FET (CMOS inverter) 12
and an input protection circuit 13 connected to the gate of this CMOS inverter 10.

The input protection circuit 13 is for preventing dielectric breakdown of the gate oxide film of the CMOS inverter 1°.
The emitter follower circuit 16 includes a type bipolar transistor 14 and a resistor 15, and a resistor 17.

An input signal is input to the base of the bipolar transistor 14. Further, the collector of the bipolar transistor 14 is connected to a power supply terminal (not shown) having a power supply voltage VDD, and the emitter is connected to a power supply terminal (not shown) having a power supply voltage VSS via a resistor 15 and a resistor 17. Connected to the gate of CMOS inverter 10.

Next, the cross-sectional structure of the emitter follower circuit 16 shown in FIG. 1 on the substrate will be explained based on FIG.

An n-type epitaxial region 26 is grown on an n+ semiconductor substrate 20, a P-well region 21 is provided within this n-type epitaxial region 26, and a p1 diffusion region 22 and an n+ diffusion region 23 are further formed inside this p-well region 21. do. The n+ semiconductor substrate 20 and the p-well region 21 form a junction, and the n1 semiconductor substrate 20 (collector), the p-well region 21 (base), and the n+ diffusion region 23 (emitter) constitute a Hpn-type bipolar transistor 14. are doing.

An input signal is guided to the P″″ diffusion region 22 in the P well region 21 by an aluminum wiring 24, and the n+ semiconductor substrate 20
A power supply voltage vDD is applied to. N diffusion region 23 is connected to aluminum wiring 25, and aluminum wiring 25 is connected to p+ diffusion region 27 formed in n type epitaxial region 26. This p″″ diffusion region 27 causes a resistance 15
is configured, and the p+ diffusion region 27 has an aluminum wiring 2.
Power supply voltage V8S is applied via 8. Therefore, the emitter of the bi7 polar transistor 14 (n+ diffusion region 23
) is connected to a power supply terminal of power supply voltage V88 via a resistor 15 constituted by a p'' diffusion region 27.

Aluminum wiring 25 is connected to CMOS inverter 10 via resistor 17 (not shown in FIG. 2). In addition,
29 is a silicon oxide film.

Next, the operation of the semiconductor integrated circuit of the above-described embodiment will be explained.

In normal operation when the input signal has a normal voltage Vin, the current between the base and collector of the bipolar transistor 14 determined by the voltage Vin is controlled. Since the magnitude of this collector-emitter current is directly taken out as the voltage drop across the resistor 15, that is, the magnitude of the emitter potential, the signal input to the gate of the CMOS inverter 10 is a converted DC level of the input voltage Vin.

Therefore, a signal whose DC level is changed by the pn junction forward voltage drop VF with respect to the input voltage Vin can be input to the gate of the CMOS inverter 10. Since the CMOS inverter 10 has a threshold of 8 (VDD"VB2) / 2 for input,
The noise margin is larger than using a bipolar inverter as disclosed in Japanese Patent Laid-Open No. 63-12158.

Furthermore, a DC level fluctuation by VF (approximately 0.6 (V) at room temperature) has little effect on the operation of the CMOS inverter 10.

Next, consider a case where a surge such as static electricity is applied as an input signal.

When the surge is of positive polarity, the input voltage Vin (>O) is input to the P1 diffusion region 22 via the aluminum wiring 24, so the potential of the P well region 21 increases, but the P well region 21 is at the VDD potential. Since it is in contact with the n+ semiconductor substrate 20 over a wide area, the potential does not become higher than the sum of the power supply voltage DD and the pn junction forward voltage drop Vp (Voo"Vp). Therefore, the p"" diffusion region 22 and If the n''' diffusion region 23 is formed sufficiently in advance, the bipolar 1
~The emitter of the transistor 14 is approximately below the power supply voltage ■DD, and the p MO that constitutes the CMOS inverter 10
The inoxide films of S F ETll and nMO5FET12 are protected.

On the other hand, when the surge has negative polarity, the potential of the p-well region 21 drops, so that the p-well region 21 and the n+ semiconductor substrate 2
0 (base-collector), p-well region 21 and n'' diffusion region 23 (base-emitter). However, if the p+ diffusion region 22 and n+ diffusion region 23 are If formed separately, most of the surge current will be transferred between the base and collector, that is, n
3 semiconductor substrate 20, p well region 21, and P'' diffusion region 22. Therefore, p+ which is connected to n+ diffusion region 23 via aluminum wiring 25
Since almost no current flows through the diffusion region 27 and no voltage drop occurs due to the resistor 15, the gate oxide film of the CMOS inverter 10 connected to the aluminum wiring 25 is protected.

The emitter follower transistor shown in FIG. 2 uses the n+ layer 20 of the epitaxial substrate as a collector region, and forms the base region in the p-well diffusion process of the CMOS inverter 10, and the emitter region in the source/drain diffusion process of the n-channel MOS transistor. Since it can be formed using a standard CMOS manufacturing process, a human power protection circuit can be realized with almost no increase in cost.

FIG. 3 shows another example of the cross-sectional structure of the emitter follower circuit 16. Components that are the same as those in FIG. 2 are designated by the same reference numerals.

In FIG. 3, a p well region 31 is provided in an n+ semiconductor substrate 20, and a p+
A diffusion region 32 and an n+ diffusion region 23 are formed. Here, the P'' diffusion region 32 has a sufficiently large area, and an aluminum input bonding pad 34 is formed on its surface.01 Semiconductor substrate 20 (collector), p well region 32 (base), and n'' diffusion region 23 (emitter) constitutes a bipolar transistor 14.

In this way, contact resistance can be reduced by directly bonding the manual bonding pad 34 to the p+ diffusion region 32 serving as the base and directly connecting it to the P well region 31. Further, by forming the input bonding pad 34 on the P3 diffusion region 32, that is, the active region, the surface size of the human power protection circuit 13 can be reduced, which also has the effect of making it possible to reduce costs. Furthermore, since the input bonding pad 34 is directly connected to the p+ diffusion region 32, heat dissipation is improved and surge resistance can be increased.

In the above-described embodiment, the case where the gate oxide film of the CMOS inverter 10 is protected is considered, but the present invention can also be applied to other CMOS type semiconductor circuits such as a CMOS AND gate provided in the input stage.

As described in detail of the G0 invention, according to the present invention, the input stage CMO is connected via an emitter follower circuit using bipolar transistors.
Since the input signal is supplied to the S semiconductor circuit, overvoltage caused by surge can be absorbed by this emitter follower circuit and dielectric breakdown of the gate of the input stage CMOS semiconductor circuit can be prevented. Noizuma 2 can secure one gin.

Furthermore, since an emitter follower circuit is used instead of an inverter circuit based on a complementary pair of bipolar transistors, an input gate with a large noise margin can be realized without complicating the manufacturing process.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a sectional view showing its structure, and FIG. 3 is a sectional view showing another structure of the semiconductor integrated circuit shown in FIG. FIG. 4 is a circuit diagram of a conventional semiconductor integrated circuit, and FIG. 5 is a sectional view showing the conventional structure of the input protection circuit shown in FIG. 4. 10: CMOS inverter

Claims (1)

[Claims] In a semiconductor integrated circuit having an input stage CMOS type semiconductor circuit to which an input signal is applied to a gate, and an input protection circuit inserted between an input terminal of the input signal and the gate, the input protection circuit is a bipolar transistor. 1. A semiconductor integrated circuit comprising an emitter follower circuit using a CMOS type semiconductor circuit, wherein an input signal is connected to the base of the bipolar transistor, and an emitter is connected to the gate of the input stage CMOS type semiconductor circuit.