JPH03101522U - - Google Patents

Info

Publication number
JPH03101522U
JPH03101522U JP1045390U JP1045390U JPH03101522U JP H03101522 U JPH03101522 U JP H03101522U JP 1045390 U JP1045390 U JP 1045390U JP 1045390 U JP1045390 U JP 1045390U JP H03101522 U JPH03101522 U JP H03101522U
Authority
JP
Japan
Prior art keywords
mounting surface
electronic circuit
groove
wiring
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1045390U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1045390U priority Critical patent/JPH03101522U/ja
Publication of JPH03101522U publication Critical patent/JPH03101522U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図〜第３図は本考案に係る電子回路の実装
基板の一実施例を示す図であり、第１図はその実
装基板の上面図、第２図は第１図の−矢視断
面図、第３図は実装基板に特定用途集積回路のチ
ツプを実装した状態を示すその断面図、第４図は
従来の電子回路の実装基板の構成図である。 １１……フイルム（実装基板）、１１ａ……載
置面、１２ａ〜１２ｄ……導体（配線）、１３〜
１６……溝部、１３ａ，１４ａ，１５ａ，１６ａ
……第１溝部、１３ｂ１４ｂ，１５ｂ，１６ｂ…
…第２溝部、１３ｃ，１４ｃ，１５ｃ，１６ｃ…
…第３溝部、１９……ワイヤ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 電子回路を載置する載置面と、該載置面の周囲
    の所定箇所に載置面と所定間隔離隔して配置され
    、電子回路の電極にワイヤを介して接続される配
    線と、を有し、可撓性部材から構成される電子回
    路の実装基板において、前記可撓性基板にコの字
    型の溝部を設け、該溝部は載置面と配線の間に形
    成された第１溝部および該第１溝部に接続され配
    線を挟み込むようにして載置面の外方に所定長延
    在する第２，３溝部から構成されることを特徴と
    する電子回路の実装基板。
JP1045390U 1990-02-05 1990-02-05 Pending JPH03101522U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1045390U JPH03101522U (ja) 1990-02-05 1990-02-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1045390U JPH03101522U (ja) 1990-02-05 1990-02-05

Publications (1)

Publication Number Publication Date
JPH03101522U true JPH03101522U (ja) 1991-10-23

Family

ID=31514022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1045390U Pending JPH03101522U (ja) 1990-02-05 1990-02-05

Country Status (1)

Country Link
JP (1) JPH03101522U (ja)

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