JPH03102265A - Maximum value detecting circuit - Google Patents

Abstract

PURPOSE:To enable direct detection of a maximum value from a digital signal by constructing a maximum value detecting circuit so that it can execute a digital processing, by connecting it directly with the same integrated circuit with a digital signal processing circuit and by detecting the maximum value thereby. CONSTITUTION:When it is assumed that n-bit data D' (expressed by a decimal number) inputted from an n-bit full adder 2 are latched in an n-bit latch 3, an output from inverters 4 numbering (n) is (2<n>-1)-D'. Now, when fresh data D come in a first input 2a of the full adder 2, the output from the inverters 4 is present in a second input 2b of the full adder 2 and the sum of the inputs to the full adder 2 turns to be (2<n>-1)-D'+D. Since the data from a first bit to an n-th bit are all 1 herein, a carry occurs in the full adder 2 when D>D'. When the fresh data are larger than the preceding data, in other words, the carry is outputted from the full adder 2 and the fresh data are latched. The data are compared sequentially in this way and the larger data are left behind.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a maximum value detection circuit that accurately detects the maximum value of audio data by processing a digital signal.

(Prior Art) When recording audio data with a recorder, the maximum output voltage value is detected in advance and the recording level is determined. Therefore, it is necessary to detect the maximum value of audio data.

FIG. 3 shows an example of a conventional maximum value detection block structure. In FIG. 3, 8 is a digital signal processing circuit (integrated circuit), 10 is a D/A converter, 11 is an analog maximum value detection circuit, 12 is an analog maximum value output terminal, and 13 is a digital signal input terminal.

The audio signal input from the digital signal input terminal l3 is output as audio data from the digital signal processing circuit 8, converted to an analog signal by the D/A converter 10, and input to the analog maximum value detection circuit 11.
The detected analog maximum value data is output from the analog maximum value output terminal I2. (Problems to be Solved by the Invention) However, in the conventional structure described above, since the digital signal is converted into an analog signal and then processed, the accuracy deteriorates, and the number of parts is reduced because dedicated hardware is required. The problem was that there were too many. The present invention solves the above-mentioned conventional problems, and aims to provide a maximum value detection circuit that can achieve maximum value detection accuracy and reduce the number of parts by directly detecting the maximum value from a digital signal. It is something. (Means for Solving Problem A) In order to achieve the above object, the present invention employs a maximum value detection circuit having a digital processing configuration, and detects the maximum value by directly connecting the maximum value detection circuit with the same integrated circuit as the digital signal processing circuit. This is how it was done.

(Function) Therefore, with the above configuration, the maximum value can be detected as a digital signal without converting the audio data, which is a digital signal, into an analog signal. Also.
A D/A converter and dedicated hardware are not required, reducing the number of parts.

(Embodiment) Figure 1 shows the configuration of a maximum value detection circuit in an embodiment of the present invention, and Figure 2 shows the block configuration of maximum value detection including the maximum value detection circuit of Figure 1. In Fig. 1, 1 is the audio data input terminal, 2 is the n
Bitful adder 28 is the first input of n-bit full adder 2, 2b is the second input, 3 is the n-bit latch, and 4 is n
5 is a carry line.

The audio data from the audio data input terminal which is the first input 2a of the full adder 2 and the second input 2b
When a carry occurs in the sum of , a carry is output to the carry line 5. Also, audio data input from the audio input terminal 1 is outputted to the n-bit latch 3 when there is a carry on the carry line 5. Latch. The output of the n-bit latch 3 enters an inverter 4 composed of n inverters, and the output of the inverter 4 enters the second input 2b of the full adder 2.

In Fig. 2, 1 is the same audio data input terminal as in Fig. 1, 6 is the maximum value output terminal, 7 is the maximum value detection circuit having the structure as shown in Fig. 1, and 8 is the same digital signal processing as in the conventional example. The circuit 9 is a digital signal processing integrated circuit that integrates a digital signal processing circuit 8 and a maximum value detection circuit 7. 13 is a digital signal input terminal. Next, the operation of the maximum value detection circuit configured as described above will be explained. In FIG. 1, assuming that n-bit data (D', expressed in decimal notation) previously input from the n-bit full adder 2 is latched in the n-bit latch 3,
The output from the inverter 4 consisting of n pieces is (2I1-1)
-D' (decimal notation). Now, new data (D) is input to the first input 2a of the n-bit full adder 2.
(Ion number display) is input, the second input 2b of the n-bit full adder 2 receives the output (2''-1)-D' from the inverter 4, and the n-bit full adder
The sum of the l-th input 2a and the second input 2b at 2 is (2'-
1) -D'+D (in decimal notation). here.
When (2”-1) is expressed as a binary number, n from the 1st bit
Since the data is all 1 up to the bit, DAD'
Then, a carry occurs in n-bit full adder 2. That is, if the new data D is larger than the previous data D', a carry is output from the n-bit full adder 2. As a result, the new data D is latched by the latch 3.

Conversely, when D'>D, no carry occurs and no carry is output. Therefore, the state in which the previous data D' is latched in the latch 3 is maintained. In this way, the maximum value of the data can be detected by sequentially comparing the data and leaving the larger data.

(Effects of the Invention) As is clear from the above-mentioned embodiments, the present invention can detect the maximum value as it is a digital signal, so that the detection accuracy can be improved. Furthermore, since it is a digital circuit and can be processed within a digital signal processing integrated circuit, it has the effect of reducing the number of parts.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a maximum value detection circuit according to an embodiment of the present invention, Fig. 2 is a block diagram of maximum value detection using the maximum value detection circuit of Fig. FIG. 3 is a block diagram of detection. 1... Audio data input terminal, 2... n
Bitful adder. 2a...first input, 2b...
...Second input, 3...n-bit latch, 4.
...Inverter (consisting of n pieces), 5... Carry line, 6... Maximum value output terminal, 7... Maximum value detection circuit, 8... Digital signal processing circuit, 9
...Digital signal processing integrated circuit, 10... D/A
converter. 11... Analog maximum value detection circuit, l2... Analog maximum value output terminal, l3... Digital signal input terminal. Figure 1

Claims (1)

[Claims] An n-bit full adder that adds n-bit data input from a first input and n-bit data input from a second input, and outputs a carry when a carry occurs; an n-bit latch that latches the n-bit data inputted to the first input by carry from the n-bit full adder; and the n-bit data of the n-bit latch output is input and the output is the n-bit latch. n inverters input to the second input of the bit full adder, the n-bit data input to the n-bit full adder and the n-bit data latched by the n-bit latch are compared, and the n-bit data input to the n-bit full adder is A maximum value detection circuit that detects the maximum value of input data by leaving the data in a latch.