JPH03102768U - - Google Patents

Info

Publication number
JPH03102768U
JPH03102768U JP1990011552U JP1155290U JPH03102768U JP H03102768 U JPH03102768 U JP H03102768U JP 1990011552 U JP1990011552 U JP 1990011552U JP 1155290 U JP1155290 U JP 1155290U JP H03102768 U JPH03102768 U JP H03102768U
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
multilayer printed
pad electrode
resin multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1990011552U
Other languages
Japanese (ja)
Other versions
JPH085580Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990011552U priority Critical patent/JPH085580Y2/en
Publication of JPH03102768U publication Critical patent/JPH03102768U/ja
Application granted granted Critical
Publication of JPH085580Y2 publication Critical patent/JPH085580Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の第１の実施例を示すポリイミ
ド樹脂多層プリント配線板への半導体素子の実装
状態を示す断面図、第２図は従来のポリイミド樹
脂多層プリント配線板上への半導体素子の実装状
態を示す断面図、第３図は本考案の第２の実施例
を示す樹脂多層プリント配線板への半導体素子の
実装状態を示す断面図、第４図は本考案の第３の
実施例を示す樹脂多層プリント配線板への半導体
素子の実装状態を示す断面図である。 １……セラミツク基板、２……感光性ポリイミ
ド樹脂、３……導体配線、４……バイヤホール、
５……半導体素子、６……接着剤、７……半導体
素子のパツド電極、８……表層導体配線のパツド
電極、９……ボンデイング用ワイヤ、１０……封
止用樹脂、１１……表層導体配線、１２，４０，
５０……高硬度の柱（金属柱）。 FIG. 1 is a cross-sectional view showing a semiconductor device mounted on a polyimide resin multilayer printed wiring board according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a semiconductor device mounted on a conventional polyimide resin multilayer printed wiring board. FIG. 3 is a cross-sectional view showing a mounting state of a semiconductor element on a resin multilayer printed wiring board showing a second embodiment of the present invention, and FIG. 4 is a third embodiment of the present invention. FIG. 2 is a cross-sectional view showing a state in which semiconductor elements are mounted on a resin multilayer printed wiring board. 1... Ceramic substrate, 2... Photosensitive polyimide resin, 3... Conductor wiring, 4... Via hole,
5... Semiconductor element, 6... Adhesive, 7... Pad electrode of semiconductor element, 8... Pad electrode of surface layer conductor wiring, 9... Wire for bonding, 10... Resin for sealing, 11... Surface layer Conductor wiring, 12, 40,
50...High hardness pillar (metal pillar).

Claims (1)

【実用新案登録請求の範囲】 半導体素子のパツド電極と多層プリント配線板
のパツド電極間をワイヤボンデイングにより接続
する樹脂多層プリント配線板において、 前記樹脂多層プリント配線板のパツド電極の下
層に接続時の外圧によつて該パツド電極が埋没し
ないように高硬度の柱を形成したことを特徴とす
る樹脂多層プリント配線板。[Scope of Claim for Utility Model Registration] In a resin multilayer printed wiring board in which a pad electrode of a semiconductor element and a pad electrode of a multilayer printed wiring board are connected by wire bonding, when the pad electrode of the resin multilayer printed wiring board is connected to the lower layer of the pad electrode of the resin multilayer printed wiring board. 1. A resin multilayer printed wiring board characterized in that highly hard pillars are formed to prevent the pad electrodes from being buried by external pressure.
JP1990011552U 1990-02-09 1990-02-09 Resin multilayer printed wiring board Expired - Lifetime JPH085580Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990011552U JPH085580Y2 (en) 1990-02-09 1990-02-09 Resin multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990011552U JPH085580Y2 (en) 1990-02-09 1990-02-09 Resin multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JPH03102768U true JPH03102768U (en) 1991-10-25
JPH085580Y2 JPH085580Y2 (en) 1996-02-14

Family

ID=31515075

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990011552U Expired - Lifetime JPH085580Y2 (en) 1990-02-09 1990-02-09 Resin multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH085580Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006120999A (en) * 2004-10-25 2006-05-11 Kyocera Corp Multilayer wiring board

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57175385U (en) * 1981-04-28 1982-11-05
JPS58219798A (en) * 1982-06-14 1983-12-21 日本電気株式会社 Multilayer circuit substrate
JPS60140897A (en) * 1983-12-28 1985-07-25 日本電気株式会社 Resin insulated multilayer board
JPS616834A (en) * 1984-06-21 1986-01-13 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57175385U (en) * 1981-04-28 1982-11-05
JPS58219798A (en) * 1982-06-14 1983-12-21 日本電気株式会社 Multilayer circuit substrate
JPS60140897A (en) * 1983-12-28 1985-07-25 日本電気株式会社 Resin insulated multilayer board
JPS616834A (en) * 1984-06-21 1986-01-13 Fujitsu Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006120999A (en) * 2004-10-25 2006-05-11 Kyocera Corp Multilayer wiring board

Also Published As

Publication number Publication date
JPH085580Y2 (en) 1996-02-14

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term