JPH03102913A - Interface for cmos circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction of a digital circuit and to improve the reliability of the operation by providing a gate circuit between an analog circuit and the digital circuit so as to simplify the constitution thereby interruption an output from the analog circuit in the standby state. CONSTITUTION:A gate circuit 24 is provided, whose signal passing condition is decided by the application of the power supply of an analog circuit 20 and when the power supply of the circuit 20 is released in the standby state the circuit 24 goes to a cutoff state and the circuit 20 and a digital circuit 23 are disconnected. Moreover, a feeding terminal 26 of the circuit 20 is connected to power voltage AVDD via an analog switch 31, and connected to ground via an analog switch 32 in the standby state. Then a high/low level from the terminal 26 and the output of the circuit 20 are fed to an AND circuit 240 and the establishment of the signal pass condition depends on the AND logic of the both, the output of the circuit 20 at the time of supplying power passes and the output of the circuit 20 is interrupted in the standby state. Thus, the output from the circuit 20 is interrupted in the standby state with simple constitution to prevent malfunction of the circuit 23 thereby improving the reliability of the circuit operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interface used in a CMOS circuit in which an analog circuit and a digital circuit are provided on a common substrate.

[Prior art] Conventionally, C, which is a hybrid of analog and digital circuits,
Although a MOSIC is used, during standby when the power supply to the analog circuit is stopped, its output becomes undefined, and as a result, there is a risk that an unnecessary switching signal may be input from the analog circuit to the digital circuit. When an unnecessary switching signal is output from an analog circuit, the digital circuit regards the switching signal as a normal input and performs an unnecessary logical operation, resulting in malfunction.

Therefore, in order to cut off unnecessary switching signals from the analog circuit side during standby, it is recommended to install, for example, an AND circuit as a gate circuit at the interface that connects the analog circuit and digital circuit to cut off unnecessary switching signals. It is being done.

[Problem to be solved by the invention]

However, when such a gate circuit is installed, in the conventional interface, one input of the AND circuit is the output of the analog circuit, and the other input is installed on the analog circuit side to detect the standby state, and the standby signal is output. In addition, it was necessary to form a signal line for this on the IC and to form a signal input terminal as an external terminal of the IC.

Therefore, the present invention aims to simplify the configuration of the CM, which prevents malfunction of the digital circuit by blocking unnecessary output from the analog circuit during standby, and improves operational reliability.
Its purpose is to provide an interface for OS circuits.

[Means for Solving the Problems] (Claim 1) That is, the CMOS circuit interface of the present invention has the following features:
Analog circuits (20
) and a digital circuit (23), a gate circuit (24) is installed to input the output of the analog circuit to the digital circuit with the power input on the analog circuit side as a signal passing condition. This is what I did.

(Claim 2) Furthermore, the interface of the CMOS circuit of the present invention includes:
Analog circuits (20
) and a digital circuit (23) (CMOS I C2), the first switch (
Power is supplied via the analog switch 31), and
When the power is cut off, the second switch (analog switch 32)
An AND circuit (240) is installed to take the logical product of the power input of the analog circuit, which has a power supply terminal (26) grounded through the analog circuit, and the output of the analog circuit.
The output of the analog circuit obtained through the circuit is input to the digital circuit.

[For production]

(Claim I) The gate circuit passes the output of the analog circuit under the condition of power input, and applies the output to the digital circuit. and,
During standby, when power supply to the analog circuit side is canceled,
When the power supply is removed, the gate circuit transitions to a cutoff state,
Analog circuits and digital circuits are separated via gate circuits.

Therefore, even if an unnecessary output is generated on the analog circuit side during standby, the input to the digital circuit side is blocked by the gate circuit, and malfunction on the digital circuit side is prevented.

(Claim 2) The power supply terminal of the analog circuit is connected to the power supply through the first switch when power is being supplied, and is grounded through the second switch during standby. That is, the power supply terminal is maintained at the power supply voltage during power supply, and shifts to the ground potential during standby.

In the AND circuit, high and low levels are applied from the power supply terminal side to one input, and the output of the analog circuit is applied to the other input, so the establishment of the signal passage condition is left to the power supply by the logical product of the two. The output of the analog circuit passes through when power is supplied, and the output of the analog circuit is cut off during standby.

Therefore, even if an unnecessary output such as a switching signal is generated on the analog circuit side during standby, it is blocked by the AND circuit where the logical product condition is not satisfied, and unnecessary input to the digital circuit is avoided, resulting in malfunction of the digital circuit. is prevented.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

FIG. 1 shows an embodiment of the CMOS circuit interface of the present invention.

CMOSIC2 has an analog circuit 2 on a common board.
0 and a digital circuit 23 that performs, for example, a logical operation based on its output, and an analog circuit 20.
A gate circuit 24 is installed between the analog circuit 20 and the digital circuit 23 as an interface for applying the switching output of the analog circuit 20 to the digital circuit 23 side.

An amplifier 200 is installed in the analog circuit 20 as a means for amplifying the analog input, and a power supply voltage A is supplied from the drive power source to the power supply terminal 26 provided as an external terminal of the IC 2.
V I,o is added. Then, during standby, conduction is established between the power supply terminal 26 and the ground point.
A switch 30 is installed as a standby circuit for shifting the potential of No. 6 to the ground level.

Furthermore, an AND circuit 240 is installed in the gate circuit 24, as an example, in order to pass the switching output of the analog circuit 20 with the power input to the analog circuit 20 as a signal passing condition.

One input terminal of this AND circuit 240 is connected to the power supply input side, the other input terminal is connected to the output part of the amplifier 200 of the analog circuit 20, and the output of the amplifier 200 is fed back to the input side of the analog circuit 20. It is now possible to do so.

The amplifier 200 is, for example, an operational amplifier as shown in FIG. 2, and is provided with a front-stage amplification section 201, a middle-stage amplification section 202, and an output-stage amplification section 203. A differential pair consisting of NMOS transistors (hereinafter simply referred to as N-channel transistors) 204 and 205 is installed in the front-stage amplifier section 201, and the N-channel transistor 204 side is set to the negative-phase input side, and the N-channel transistor 205 is set to the positive-phase input side. and the gate of the N-channel transistor 2o4 is connected to the negative phase input terminal 206 and the N-channel transistor 20
The gate of No. 5 is connected to the positive phase input terminal 207. An N-channel transistor 208 as a constant current source is connected to the source side of the N-channel transistors 204 and 205, and a current mirror circuit is connected as an active load to the drain side of the N-channel transistors 204 and 205.
-MOS} transistors (hereinafter simply referred to as P-channel transistors) 209 and 210 are installed. A differential pair consisting of P channel transistors 21L212 is installed in the middle stage amplifier section 202, and the P channel transistors 21
1, the power supply voltage AVoo is applied to the source side of 212,
Further, an N-channel transistor 213 having a constant current source whose gate is directly connected to the N-channel transistor 208 is connected to the drain side. A diode-connected P-channel transistor 215 is connected between the positive voltage line 214 connected to the power supply terminal 26 and the gates of the N-channel transistors 208 and 213.
A diode-connected N-channel transistor 216 is connected between the gate of each N-channel transistor 208 and 213 and the ground point, and each transistor 215 and 2
16 sets the gate potential of the N-channel transistors 208 and 213. In addition, the output stage amplification section 20
3 is composed of P channel transistors 217 and 218, N channel transistors 219 and 220, and a phase compensation capacitor 221, and N channel transistor 2
19 and 220 form a current "s" circuit. Therefore, the positive phase input terminal 207 and the negative phase input terminal 206
The analog input applied to is amplified by the front-stage amplification section 201, the middle-stage amplification section 202, and the output-stage amplification section 203, and the amplified output is taken out as the switching output V0 to be input to the digital circuit 23.

The digital circuit 23 to which this switching output V0 is applied via the gate circuit 24 is provided with a power supply terminal 28 for receiving power from a drive power source separate from the analog circuit 20 so that its operation does not affect the analog circuit 20. The power supply voltage ■ is a separate system from the power supply voltage AVo of the 20 analog circuits. , has been added.

With the above structure, when power is supplied, the switch 30 is opened and the power supply voltage A V o is applied to the power supply terminal 26, while the power supply voltage vl)D is also applied to the power supply terminal 28. As a result, the analog circuit 20, digital circuit 23, and gate circuit 24 become operational.

Therefore, when an input signal is applied to the amplifier 200, it is amplified by the amplifier 200, and its amplified output is a switching output V. is added to the gate circuit 2-4. The AND circuit 240 receives the power supply voltage A applied to the power supply terminal 26.
Since H level input is added by VDI1,
The AND condition is satisfied and the switching output V is obtained by the analog circuit 20. is applied to the digital circuit 23 through the AND circuit 240. Then, in the digital circuit 23, a predetermined logical operation is performed based on the switching output v0.

Also, during standby, the power supply voltage AVI, for the power supply terminal 26. is released, the switch 30 is closed, and the power supply terminal 26 is held at the ground potential. At this time, the amplifier 200 stops operating and the input of the AND circuit 240 shifts to L level, so even if an unnecessary output due to the undefined state of the analog circuit 20 is applied to the gate circuit 24, the AND condition is not satisfied. Because it does not do so, it prevents its output from passing through. Therefore, during standby, even if the analog circuit 20 issues an unnecessary switching signal, the analog circuit 20 and the digital circuit 23 are cut off by the gate circuit 24, so that malfunctions on the digital circuit 23 side are prevented.

Next, FIG. 3 shows a specific example of the configuration of the switch 30 installed as a standby circuit at the interface of the CMOS circuit shown in FIG.

That is, the power supply terminal 26 is connected between the power supply side and the power supply terminal 26.
An analog switch 31 is installed as a first switch for switching between supplying and cutting off the power supply voltage AVDD,
Furthermore, an analog switch 32 is installed between the power supply terminal 26 and the ground point as a second switch for grounding the power supply terminal 26 during standby.

The switch input S1 is applied to the positive phase input section of the analog switch 3l through the input terminal 33, and the switch input S1 is inverted and applied to the negative phase input section of the analog switch 3l through the inverter 34. Further, the switch input S2 is applied to the positive phase input part of the analog switch 32 through the input terminal 35, and the switch input Sz is inverted and applied to the negative phase input part of the analog switch 32 through the inverter 36.

With this arrangement, during non-standby, a high (H) level switch input S, is applied to the input terminal 33, and a low (L) level switch input S2 is applied to the input terminal 35.

At this time, the analog switch 31 is in a conductive state, and the other analog switch 32 is in a cut-off state. Therefore, the power supply voltage AVDI1 is applied to the power supply terminal 26 through the analog switch 3l, and the amplifier 200 becomes operational. As a result, the necessary amplification operation is performed in the amplifier 200, and the digital circuit 2
At 3, a predetermined logical operation is performed.

Further, during standby, an L level switch input S is applied to the input terminal 33, and an H level switch input S2 is applied to the input terminal 35. At this time,
The analog switch 3l is turned off, and the other analog switch 32 is turned on. Therefore, the supply of the power supply voltage AVno to the power supply terminal 26 is terminated, and at the same time, the power supply terminal 26 is grounded through the analog switch 32 and held at the ground potential.

In this way, the power supply is switched by switching the analog switch 3l, and at the time of standby, the power supply terminal 26 is held at the ground potential through the analog switch 32, so the standby current consisting of the bias current etc. flowing through the amplifier 200 is erased. , A of the AND circuit 240
The amplifier 200 is in an undefined state by preventing the ND condition from being satisfied.
The switching output V emitted from. prevent the passage of
The reliability of the operation of the digital circuit 23 is increased.

Next, FIG. 4 shows a specific circuit configuration example of the interface of the CMOS circuit shown in FIG.

A P-type semiconductor substrate 40 is used as a common substrate forming the analog circuit 20, digital circuit 23, and gate circuit 24.
For example, a P-channel transistor 218 and an N-channel transistor 220 on the amplifier 200 side are formed on this semiconductor substrate 40, and a P-channel transistor 231 and an N-channel transistor 231 on the digital circuit 23 side receiving the output of this amplifier 200 are formed. N-channel transistor 2
32 is prominent. That is, in the surface layer of the semiconductor substrate 40, an N-well 401 is formed as an N-type region that dominates the shape of the P-channel transistor 218 by diffusion of N-type impurities, etc.
P-channel transistor 23 due to diffusion of type impurities, etc.
An N-well 402 is used as an N-type area that controls the type-1 area.

In the N-well 401, a source 403 and a drain 404 of a P-channel transistor 218 are formed by selective shaping of the P-type region, and a channel stopper 405 is formed by selective shaping of the N-type region. , source 403
and the gate 40 opposite the channel between the drain 404
6 is prominent. This P channel transistor 21
8 adjacent to N channel 1 by diffusion of N type impurities, etc.
- Source 407 and drain 408 of transistor 220
is formed, and the source 407 and N well 401
A channel stopper 409 is formed between the source 407 and the drain 4 by diffusion of P-type impurities, etc.
A gate 410 is formed opposite the channel between 08 and 08.

Furthermore, on the N-well 402 side, a source 413, a drain 4, a channel stopper 415, and a gate 416 of a P-channel transistor 231 are formed, and adjacent to this N-well 402, a source 417 of the N-channel transistor 232, Drain 418, channel stopper 41
9 and gate 420 are similarly shaped.

and the source 403 of P-channel transistor 218
The channel stopper 405 is commonly connected to the power supply terminal 26 through a wiring conductor 426, and is also connected to the analog switches 3 and 32 through the power supply terminal 26, so that the power supply voltage A V o is supplied through the analog switch 31 during non-standby. . is applied and also grounded through the analog switch 32 during standby.

The analog switch 31 is composed of a transfer gate in which the sources and drains of the N-channel transistor 311 and the P-channel transistor 312 are connected in common.
A switch input S1 is connected to the gate of S1 through an input terminal 33.
is applied to the gate of the P-channel transistor 312, and its switch input SI is inverted by the inverter 34 and applied to the gate of the P-channel transistor 312. Further, the analog switch 32 installed between the power supply terminal 26 and the ground point is a transfer switch that commonly connects the sources and trains of the N-channel transistor 321 and the P-channel transistor 322, similarly to the analog switch 3l. Suinochi input S2 is applied to the gate of the N-channel transistor 321 through the input terminal 35,
Further, the switch input S2 is inverted by an inverter 36 and applied to the gate of the P-channel transistor 322.

Further, the source 407 and channel stopper 409 of the N-channel transistor 220 are commonly grounded through a wiring conductor 422.

On the other hand, the source 413 and channel stopper 415 of the P-channel transistor 231 on the digital circuit 23 side are
They are commonly connected by a wiring conductor 423, and are also connected to a power supply installed on the digital circuit 23 side to which a power supply voltage . In addition, the source 417 of the N-channel transistor 232 and the channel stopper 419
are commonly connected through a wiring conductor 424 and grounded.

If such a structure is adopted, input terminal 3 will be
When an H-level switch input SI is applied to input terminal 3 and an L-level switch input S2 is applied to input terminal 35, the N-channel transistor 311 and P-channel transistor 312 on the analog switch 31 side become conductive, and the N-channel transistor on the analog switch 32 side becomes conductive. 321 and P-channel transistor 322 are turned off. Therefore, the power supply voltage AV no is applied to the power supply terminal 26, the power supply voltage AVDD is applied to the source 403 and the channel stopper 405 of the P-channel transistor 218, and the P-channel transistor 218 on the analog circuit 20 side becomes operational. As a result, the amplifier 200 performs the necessary amplification operation, and its output is applied to the digital circuit 23.

In addition, during standby, the switch input 31 is at L level to the input terminal 33, and the switch input S is at H level to the input terminal 35.
2 is added, the N-channel transistor 321 and P-channel transistor 32 on the analog switch 32 side
2 is in a conductive state, and the N-channel transistor 311 and the P-channel transistor 312 on the analog switch 31 side are in a cut-off state. Therefore, the power supply voltage AVI,I, applied to the power supply terminal 26 is released, and the source 403 of the P-channel transistor 21B and the channel stopper 405 are grounded through the N-channel transistor 321 and the P-channel transistor 322, and are held at the ground potential. Therefore, during standby, the standby current consisting of the bias current etc. on the amplifier 200 side is reliably erased, and the AND condition of the AND circuit 240 is prevented from being established, and malfunctions of the 23 digital circuits are prevented, thereby improving the reliability of operation. is enhanced.

[Effects of the Invention] As explained above, according to the present invention, the following effects can be obtained.

(a) After cutting off unnecessary output from the analog circuit side with a simple precaution, using the power input as a signal passing condition,
During standby, it prevents malfunction of digital circuits and
The reliability of operation can be increased without being restricted by pins or operating modes.

(b) The first power supply to the power supply terminal of the analog circuit.
In addition to switching with the switch, the second
The power supply terminal is grounded through the switch, and the transition to the ground level prevents the AND condition of the AND circuit installed as a gate circuit, and cuts off unnecessary output from the analog circuit. The reliability of circuit operation can be improved.

[Brief explanation of drawings]

1 is a circuit diagram showing an embodiment of the CMOS circuit interface of the present invention; FIG. 2 is a circuit diagram showing a specific example of the circuit configuration of an amplifier in the CMOS circuit interface shown in FIG. 1; 3 is a circuit diagram showing a specific example of the circuit structure of the CMOS circuit interface of the present invention, and FIG. 4 is a diagram showing a specific example of the circuit structure of the CMOS circuit interface shown in FIG. 3. be. 2...CMOS IC (CMOS circuit) 20...
Analog circuit 23...Digital circuit 24...Gate circuit 240...AND circuit 26...Power supply terminal 31...Analog switch (first switch) 32...
...Analog switch (second switch) 40...Semiconductor substrate←111τ--111--120 Analog circuit Figure 1 (An example of interface of CMOS circuit)-186
-88-

Claims (1)

[Claims] 1. In a CMOS circuit in which an analog circuit and a digital circuit are provided on a common substrate, the output of the analog circuit is input to the digital circuit using a power input on the analog circuit side as a signal passing condition. A CMOS circuit interface characterized by having a gate circuit installed therein. 2. A CMOS circuit in which an analog circuit and a digital circuit are installed on a common substrate, which is provided with a power supply terminal that is supplied with power through a first switch and is grounded through a second switch when the power is cut off. A CMOS circuit characterized in that an AND circuit is installed to take a logical product of the power input of the analog circuit and the output of the analog circuit, and the output of the analog circuit obtained through the AND circuit is input to the digital circuit. interface.