JPH0310355A - Common bus priority control method - Google Patents

Abstract

PURPOSE:To efficiently operate a common bus by changing the time distribution for giving of the priority of a bus in accordance with the dynamically changing frequency in common bus use of each bus master. CONSTITUTION:The processor of a common bus control part 21 rewrites time distribution data for giving of the priority to individual bus masters in a memory 5 based on a prescribed program in accordance with change requests of common bus acquisition timing from bus masters 22 to 2. After this rewrite, time distribution data in the memory 5 is successively cyclically accessed by a counter 3, and the output of the memory 5 at this time is used as an acquisition permitting signal of a common bus 31 to each bus master. Thus, the common bus is efficiently used because the common bus control part 21 manages the priority control of the common bus 31 is accordance with frequencies in common bus use of bus masters.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a method of priority control of a common bus in a system that gives priority to a common bus by time sharing to a plurality of path masks. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

[Conventional technology]

Conventionally, systems that perform priority control of common buses using time sharing have fixed hardware such as switching boards and ROM.
Many have regulations governing the time during which priority can be obtained.

[Problem to be solved by the invention]

However, with the above-mentioned conventional technology, the time during which priority can be acquired for the common bus is fixed by the hardware, so it cannot cope with the dynamically changing frequency of use of the common bus by each bus master, and as a result, the overall common The disadvantage was that the efficiency of bus use was not improved. Therefore, in order to solve this problem, the present invention uses a counter and a rewritable memory in the common bus control unit and allocates the memory output to manage the time during which priority can be acquired in the priority control of the common bus. An object of the present invention is to provide a common bus priority control method in which memory can be programmably rewritten by a processor of a common bus control unit.

[Means to solve the problem]

In order to solve the above problems, the method of the present invention is to change the time allocation of bus masters in a system that gives priority to a common bus (such as 31) to bus masks (22 to 24, etc.) in time sharing. In order to switch the time allocation for giving priority to each bus mask according to requests, a counter (such as 3) and a rewritable memory (such as 5) are prepared, and these are connected to a common bus control unit (such as 21). )'s processors (such as 1) collectively manage the bus masters to give them priority according to the frequency of use of the common bus.

[For use]

The processor of the common path control unit rewrites the time allocation data for giving priority to each bus master in the memory based on a predetermined program in response to a request to change the common bus acquisition timing from the bus mask. The time allocation data in the memory is cyclically accessed in sequence, and the output of the memory at this time is used as a common bus acquisition permission signal for each bus mask.

【Example】

The present invention will be explained in detail below based on FIGS. 1 to 5. First, FIG. 2 shows an example of a system configuration to which the present invention is applied. In this system, the main purpose of each bus mask 22 to 24 is to access the common memory 25 via the common bus 3I. Here, the common path control unit 21 has the role of giving permission to use the common bus 31 (common bus acquisition permission signal) to each of the bus masters 22 to 24. In the following, for convenience of explanation, the bus masks 22 to 24 will also be named bus master (A) to bus master (C), respectively. As an example in FIG. 5, bus master (B) 23 acquires the bus,
Indicates when to use and release. Each of the bus masters 22 to 24 has a common bus control section 21.
When the internal request signal BRQ requesting the common bus 31 is output to the respective bus masters, the common bus acquisition permission signals E (BA, EB, EC) given from the common bus control unit 21 to each bus master are valid and the other bus masters are The common bus 31 can be acquired by validating the bus busy signal BBSY only when the common bus 3■ is not used (the bus busy signal EESY in FIG. 5 is invalid). Now, when the timing of the acquisition permission signals EA to EC of the common bus 31 as shown in FIG. )23 has made the decision. In that case, the bus mask (B) is the common bus control unit 21 (
A request to change the common bus acquisition timing is transmitted to the processor 1), which will be described later, via the common bus 31 using a command or the like. Having received the request, the common bus control unit 21 (processor 1) sets a new common bus acquisition permission timing as shown in FIG. 4, taking into account requests from other bus masks, and To perform priority control according to the frequency of bus use. FIG. 1 shows an embodiment of the hardware configuration of the common bus control section 21 for programmably rewriting the timing. Processor 1 uses processor address bus 1 to set the timing change value of bus acquisition permission signal E.
1. The memory selection signal 12 is sent to the memory 5 via the decoder 2.
to select memory 5. The address signal inputted to the terminal B of the address selector 4 by the selection signal 12, that is, the address (signal) from the processor 1
is input into the memory 5. The processor 1 makes one of the processor data buses 14 valid for that address, that is, for any time 10 to t7 shown in FIG. 4, to indicate which bus mask is given priority. The output data is stored in the memory 5 via the buffer 7. During this time, buffer 6 is not enabled. When the access to the memory 5 by the processor 1 is completed, the memory selection signal 12 is turned off, and the address selector 4 starts the 3-bit counter 3, which repeatedly increments from 0 to 7 at a constant cycle. The output, that is, the input signal at terminal A is given as an atlus to the memory 5. The memory 5 corresponds to the given address (signal) (0 to 7) and the processor 1
The data written in the above manner is output from the buffer 6 (as a signal indicating the timing at which the bus mask for an arbitrary period of time can acquire priority in response to the common bus acquisition timing change request). In this way, the common bus control unit 21 manages the priority control of the common bus 31 according to the frequency of use of the common bus in the bus mask, thereby making it possible to efficiently utilize the common bus.

【Effect of the invention】

According to the present invention, it is possible to change the time allocation for giving bus priority according to the frequency of use of the common bus for each bus mask, which changes dynamically, and as a result, efficient operation of the common bus is possible. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of a common bus control unit as an embodiment of the present invention, FIG. 2 is a block diagram of the overall system to which the present invention is applied, and FIGS. 3 and 4 are respective common bus acquisition permissions. FIG. 5 is a time chart showing different examples of timing allocation. FIG. 5 is a time chart showing an example of acquiring a common bus.

Claims (1)

[Claims] 1) In a system that gives priority to a common bus to multiple bus masters through time sharing, the counter is rewritten so that the time allocation that gives priority to each bus master can be switched in response to a bus master's time allocation change request. A common bus priority control method, characterized in that a processor of a common bus control section collectively manages the available memory and gives priority according to the frequency of use of the common bus by a bus master.