JPH03105647A - Transfer system for request - Google Patents

Abstract

PURPOSE:To curtail the number of gates and to execute a request control in a storage control part at a high speed, and to shorten the machine cycle by executing a test request sending-out control in one cycle, and using a part of an interface register in common. CONSTITUTION:A test request of one cycle from a test request control circuit 2 is sent out by controlling whether the next request read out of a test request stack 1 is sent out, or the same request as that which is sent out in the previous time is sent out, by a test request receiving response signal E from a one-cycle request control circuit 5. Accordingly, an interface register in the one-cycle request control circuit 5 can be used in common. In such a way, the number of gates of the one-cycle request control circuit can be curtailed, and the machine cycle can be shortened due to a decrease of a delay time of the control.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to reduce the number of gates, speed up request control within the storage control unit, and shorten the machine cycle with respect to a transfer method for requests sent to a storage unit in a computer system. year. A test that sends test requests taken out from the test request stack to the test request stack that stores test requests, the 2-cycle request control circuit, the 1-cycle request control circuit, and the 2-cycle request control circuit and the 1-cycle request control circuit. Equipped with a request control circuit. Selecting the requests in the 2-cycle request system 11 circuit and the requests in the 1-cycle request control circuit on the basis of priority. It has a configuration that performs priority control for sending data to the main storage device, etc.

[Industrial application field]

The present invention relates to a transfer method for requests sent to a storage unit in a computer system, and particularly to a transfer method for test requests. As computer systems have become larger in recent years, the number of devices that send requests to a single storage device has increased, but in order to meet the demands for smaller and faster computer systems. By sharing registers and the like within each device, it is necessary to reduce the number of LSIs and the number of signal lines between LSIs.

[Conventional technology]

Test requests sent to storage in conventional computer systems are mainly needed for the following two purposes. One is to send a pseudo request in place of a device that sends a two-cycle request such as a central processing unit W (CPU), and to test storage control without a device that sends a two-cycle request. , and the other is used for sending requests from SvP during normal system operation, requests for storage device patrol, etc. On the other hand, conventional storage control units have one interface register for each request source device. For this reason, the test request sending device. It was sufficient to send only 2-cycle requests. However, due to parallelization of central processing units, etc. As the number of request sending devices increases, it is necessary to have a large number of interface registers in the storage control unit, and it is difficult to share the interface registers for test requests during normal operation with those for other devices. This was not possible because the request was a two-cycle request.

Therefore, it is necessary to have an interface register for test requests. Due to an increase in the number of gates (number of L31), an increase in the number of output branches in the logic circuit of the request control part in the memory system 1rj section, and an increase in the number of human resources. The delay time in request control increased, making it difficult to shorten machine cycles. To explain specifically. If you have separate interface registers for the MCU and the tester (SVP request) as in conventional circuits, the LS
In the division of I, L of the part called ADRS SEL
The number of SIs will have to be increased by one just because of the lack of signal lines. but. It is not desirable to increase the number of LSIs because the number of branches of control signals input to the LSI and the number of signal lines from the LSI to the priority control circuit increase the amount of signal delay.

Also, a request from the MCU is a 1-cycle request and requires 9 interface registers (PREPORT).
After receiving the signal, it controls l cycles. Therefore, if the request from TESTER is 2 cycles. It is necessary to change the control after receiving it in the interface register for 2 cycles. If you do this. Control becomes very difficult. The delay will also be severe. But T
If the request from ESTER takes one cycle, control after receiving it in the interface register will be easier. [Problems to be Solved by the Invention] The present invention achieves this by performing test request sending control in one cycle during normal system operation. By sharing some interface registers. Aimed at reducing the number of gates and increasing the speed of data transfer control within the memory control section. The purpose is to shorten machine cycles. [Means for solving the problem] Figure 1 is a diagram explaining the principle of the present invention. In the figure, 1 is . This is the test request stack. It stores test requests in advance. 2 is. This is a test request control circuit that controls the sending of test requests. 3 is. This is a priority control circuit within the memory control unit. Prioritizes requests from various devices based on request information. Something that accesses the memory section. 4 is. This is a 2-cycle request control circuit in the storage control unit, and is a device that sends one request in 2 cycles (
A request (A) from a central processing unit, etc.). It is received by an interface register, one for each device, held until it is selected by the priority control circuit 3, and then notifies the request exit source device of the waiting status B (C). 5 is. This is a 1-cycle request control circuit in the storage control unit, which selects a test request and a 1-cycle request (B) from another device, receives it in an internal interface register, and holds it until it is selected by the priority control circuit 3. ,That ambush J! I (D) and. This is to notify the request source device of a response signal (E) indicating that a test request has been selected and set in the interface register. is prevented. 1 because it does not follow legitimate priorities.
Machine cycles can be shortened by reducing the number of gates (LSIs) in the cycle request control circuit and by reducing control delay time. [Function] In the present invention, as shown in FIG. 1, one cycle of test request transmission from the test request control circuit is as follows. By the test request reception response signal from the 1-cycle request control circuit. Whether to send the next request read from the test request stack. This is done by controlling whether to send the same request as the previous one, and it becomes possible to share the interface register in the 1-cycle request control circuit, which was not possible with a 2-cycle test request. In other words, in the case of a 2-cycle test request, the latter! When a 1-cycle request (B) is sent from an external device during a cycle. Setting a 1-cycle request (B) to an interface register [Embodiment] Fig. 2 is a diagram showing an embodiment of the present invention, and shows a request transfer control section. In the figure. Components that are the same as those shown in Figure 1 are indicated by the same symbols. la is the stack address register of test request stack l. Register section 1b holds the address for storing requests (RAM may be used), 2a is the SvP interface control circuit of the test request control circuit 2 and receives signals from svp, 2b is the test This is a request read control circuit, which uses the stack address selection circuit 2c and stack address basic 2d to control the address of the test request to be read from the test request stack 1, and the request read which holds the read data from the register section 1b. Controls the settings of register 2e (clock control), etc. 2r is a test request sending control circuit.
Is the test request an l-cycle request? 2
2g is an l-cycle test request recognition register that determines whether it is a cycle request, recognizes the destination, and controls the transmission timing of the test request using the transmission register setting signal 27 from the test request read control circuit 2b. can be. 2h is the l-cycle delay register of 2g. 2j is a 2-cycle delay register of 2g, which indicates that the request sent to the test request sending circuit is a 1-cycle test request, and 4a is a 2-cycle delay register of 2g. This is a 2-cycle request input selection circuit for the 2-cycle request control circuit 4. 4b is a 2-cycle request interface register that holds the request selected by the 2-cycle request input selection circuit; 4C is a 2-cycle It is a request selection wait control circuit,
It maintains the waiting state until it is selected by the priority control circuit 3.
5a is a device that notifies the request sending device of its status. This is the 1 cycle request manual selection circuit of the 1 cycle request control circuit, and the 1 cycle request}B
5b is a 1-cycle request interface register that holds the request selected by the 1-cycle request input selection circuit; 5C is a 1-cycle request selection wait control circuit. Yes, it remains in a waiting state until it is selected by the priority control circuit 3. It notifies the request sending device of its status and a response signal upon receiving the test request.

An example of operation is shown below. FIG. 3 is a time chart of request transfer control using the embodiment shown in FIG. 2. A command from SvP is input manually to the SVP interface control circuit 2a, 6 it is decoded, a start signal 21 is issued, and the transfer of the test request is started. The test request read control circuit 2b is . Upon receiving the activation signal 21, a clock control signal 25 for the stack address register la and stack address basic 2d is generated.
Send. Moreover, the select count up signal 24 has fallen, the stack address ゜0゜ is set in 1a and 2d, and the request from the register section 1b of the stack (
address, opcode, requester ID, etc.). At the same time as this. Raise the clock control signal 26 and select count up signal 24. Clock control signal 26
Request test request by request read register 2
e, and clock control signal 25 and transmission control signal 2
Raise 7. If the request is 2 cycles, a 2-cycle interface signal 28 is sent, and if it is 1 cycle, a 1-cycle interface signal 29 is sent. At this time, the 2-cycle request BUSY signal Cl has not risen. The clock control signal 25 is raised, the stack address "2" is sent, and the 1-cycle request (2) is read into the request read register 2e, but since the BUSY signal CI is raised, the clock control signal 25 is not raised. , and the l cycle request (1) from the interface signal 28 is extended by one cycle and sent for three cycles.

When a 2-cycle request is made, the exit control signal is raised only for l cycles, and the same request continues to be sent for at least 2 cycles, but when it is a 1-cycle request, it is raised for 2 cycles, and the request is sent for only 1 cycle. Ru. The sent request is received by the 2-cycle request interface register 4b or the 1-cycle request interface register 5b. As shown in Figure 3, the request (0) is held for three cycles because the BUSY signal has risen by one cycle. Request (1) is BUSY
Since the signal is not rising, it is held for two cycles. Further, after receiving the 1-cycle request (2) at 5b, a response signal El is sent out. According to the timing of the response signal. and a recognition signal 23 indicating that the sending request is a one-cycle test request, and the response signal.
Raise the reception completion signal 2a in the test request readout control circuit. Read out the next request (3). Request (3) is sent in the next cycle, but 1
The cycle request input selection circuit 5a sets the request (6>) input from Bl in the interface register 5b, and the response signal does not go up.The reception completion signal also does not go up.The request (3>) is sent again. Also, 2b is a signal in the test request readout control circuit.It is a request address sending control signal.2
c is a store data transmission control signal. [Effects of the invention] Keyaki explained above. According to the present invention, the receiving interface register in the storage control unit for one cycle of test requests can be shared, and the amount of material can be increased due to an increase in the number of LSIs. Machine cycles can be shortened by reducing the delay time of request transfer control by reducing the number of output branches and the number of inputs to logic circuits. It greatly contributes to improving the performance of the request forwarding section.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a diagram showing the structure of an embodiment of the present invention, and Fig. 3 is a time chart of request transfer control according to the structure of the embodiment of the present invention. In the figure, l: 2: 3: 4: 5: la: ltz 2a: 2 b = 2C: 2dj 2e: 2]: 2g = 2h: 2j: 4a: 4b: Test request stack. Test request control circuit. Priority control circuit. 2-cycle request control circuit. 1 cycle request control circuit, stack address register, register section. SVP interface control circuit. Test request read control circuit. Stack address selection circuit, stack address basic. Request read register. Test request sending control circuit. l-cycle test request recognition register 5 l-cycle delay register. 2 cycle delay register. 2-cycle request input selection circuit, 2-cycle request interface register, 4C: 2-cycle request selection wait control circuit, 5a:
1 cycle request input selection circuit. 5b: 1 cycle request interface register.

Claims (2)

[Claims] (1) A test request stack that stores test requests, a 2-cycle request control circuit, a 1-cycle request control circuit, and requests from arbitrary entries in the test request stack are read and tested to the 2-cycle request control circuit. The test request control circuit is equipped with a test request control circuit that sends a test request as a two-cycle request or a test one-cycle request to a one-cycle request control circuit, and the two-cycle request control circuit remains on for two cycles sent from the first external device. The 1-cycle request control circuit holds a certain 2-cycle request or a 2-cycle request for testing sent from the test request control circuit, and the 1-cycle request control circuit holds a 1-cycle request sent from a second external device that is in an on state for 1 cycle. It holds requests or test one-cycle requests sent from the test request control circuit, selects requests in the two-cycle request control circuit and requests in the one-cycle request control circuit based on priority, and selects the requests in the two-cycle request control circuit and the requests in the one-cycle request control circuit, and A request transfer method characterized by priority control for sending requests to a storage device, etc. (2) In claim (1), when the test request control circuit sends a test request to the 2-cycle request control circuit, a busy signal from the 2-cycle request control circuit is referenced, and the busy signal indicates that the circuit is busy. When the test request is in the on state, the test request is sent until the busy signal becomes the off state indicating vacancy, and when the test request control circuit sends the test request to the one cycle control circuit, the test request is sent to the one cycle control circuit. A request transfer characterized in that when the response signal sent from the device is in an on state indicating busy, the next test request is sent, and on the other hand, when the response signal sent from the device is in an off state indicating free, the same test request is sent. method.