JPH03108362A - Circuit board for mounting semiconductor, and manufacture thereof - Google Patents

Circuit board for mounting semiconductor, and manufacture thereof

Info

Publication number
JPH03108362A
JPH03108362A JP1245036A JP24503689A JPH03108362A JP H03108362 A JPH03108362 A JP H03108362A JP 1245036 A JP1245036 A JP 1245036A JP 24503689 A JP24503689 A JP 24503689A JP H03108362 A JPH03108362 A JP H03108362A
Authority
JP
Japan
Prior art keywords
conductor circuit
resin
circuit board
semiconductor device
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1245036A
Other languages
Japanese (ja)
Other versions
JP2726515B2 (en
Inventor
Chiharu Watanabe
千春 渡辺
Takeo Iguchi
建夫 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denka Co Ltd
Original Assignee
Denki Kagaku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denki Kagaku Kogyo KK filed Critical Denki Kagaku Kogyo KK
Priority to JP24503689A priority Critical patent/JP2726515B2/en
Publication of JPH03108362A publication Critical patent/JPH03108362A/en
Application granted granted Critical
Publication of JP2726515B2 publication Critical patent/JP2726515B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、導体回路の少なくとも部品塔載部分を除Aて
樹脂状で被覆して耐電圧の低下を防止し、しかもダイオ
ード、トランジスター、サイリスタトライアック等のパ
ワー半導体装置を塔載した際の高放熱性にもすぐれた半
導体塔載用回路基板及びその製造方法に関するものであ
る。
Detailed Description of the Invention (Industrial Field of Application) The present invention provides a method for coating a conductor circuit with a resin, excluding at least the part on which the components are mounted, to prevent a drop in withstand voltage. The present invention relates to a circuit board for mounting a semiconductor tower which has excellent heat dissipation when a power semiconductor device such as a triac is mounted thereon, and a method for manufacturing the same.

(従来の技術) 従来、回路基板にはアルミナ、窒化アルミニウム、ベリ
リア、シリコーンカーバイド等のセラミックス層を持っ
たアルミニウム板、銅板、鉄板及びステンレス板のセラ
ミックス基板する^はアルミニウム、銅、鉄及びステン
レス等に樹脂又は無機充てん剤を含有した樹脂絶縁層を
設けた金属ベース基板が使用されて論る。そしてこの回
路基板は第4図に示すように導体回路4に気泡12が付
着した夕、回路基板作成時に半田付着防止のため半導体
装置、抵抗体及びリード端子部分以外の導体回路部分に
半田レジストを全yjJ塗布し、しかも第6図に示すよ
りに例えば導体回路4間に半田レジスト13を塗布し半
田の流入を防止する使用万法もあるが、このような方法
であっても導体回路4としての一部が露出して^るため
に電界集中が起り、導体回路4周囲の絶縁層が除々に破
壊されて絶縁不良を発生させて耐電圧の低下を招くとさ
れてhる。また第5図のように中空パッケージの場合に
は、中空内で放電現象が発生し、この際発生したプラズ
マによって絶縁層表面が酸化し、この現象が繰り返され
ることにより、絶縁層が薄肉化して絶縁不良が生じ耐電
圧が低下する原因となる。
(Prior art) Conventionally, circuit boards have been made of ceramics such as aluminum plates, copper plates, iron plates, and stainless steel plates with ceramic layers such as alumina, aluminum nitride, beryllia, and silicone carbide. A metal base substrate provided with a resin insulating layer containing a resin or an inorganic filler is used. As shown in FIG. 4, when bubbles 12 were attached to the conductor circuit 4, this circuit board was made by applying solder resist to the conductor circuit parts other than the semiconductor device, resistor, and lead terminal parts to prevent solder adhesion when making the circuit board. There is also a method of applying solder resist 13 between the conductor circuits 4 to prevent the inflow of solder, as shown in FIG. Because a portion of the conductor circuit 4 is exposed, electric field concentration occurs, and the insulating layer around the conductor circuit 4 is gradually destroyed, causing insulation failure and a decrease in withstand voltage. In addition, in the case of a hollow package as shown in Figure 5, a discharge phenomenon occurs within the hollow space, and the plasma generated at this time oxidizes the surface of the insulating layer, and as this phenomenon is repeated, the insulating layer becomes thinner. This may cause insulation failure and a drop in withstand voltage.

(発明が解決しようとする課題) 本発明はかかる欠点を解決するものであり、回路基板の
導体回路を部品塔載部分を除^て樹脂状物で被覆して気
泡を除去し、使用時の電界集中全緩和することにより、
耐電圧の低下を防止すると共に絶縁層の厚さを極力おさ
えることにより放熱性の低下も防ぐことができること金
兄い出し、半導体塔載用回路基板及びその製造方法全完
成するに至った。
(Problems to be Solved by the Invention) The present invention solves these drawbacks by covering the conductor circuit of the circuit board with a resin-like material except for the parts mounting part to remove air bubbles, and to prevent air bubbles from forming during use. By completely relaxing the electric field concentration,
It was discovered that it was possible to prevent a decrease in withstand voltage and also to prevent a decrease in heat dissipation by minimizing the thickness of the insulating layer, and a circuit board for mounting semiconductors and a method for manufacturing the same were completed.

(課題を解決するための手段) すなわち本発明は、導体回路を設けた絶縁基板の前記導
体回路の少なくとも周縁部分に樹脂又は無機充てん剤含
有樹脂絶縁物t−被覆してなることを特徴とし、葦だ前
記導体回路の露出部分に半導体装置等を塔載なることを
特徴とする半導体塔載用回路基板及びその製造方法であ
る。
(Means for Solving the Problems) That is, the present invention is characterized in that an insulating substrate provided with a conductor circuit is coated with a resin or an inorganic filler-containing resin insulator T-coating on at least the peripheral portion of the conductor circuit, A circuit board for mounting a semiconductor device, and a method for manufacturing the same, characterized in that a semiconductor device or the like is mounted on the exposed portion of the conductor circuit.

以下図面により本発明の詳細な説明する。The present invention will be explained in detail below with reference to the drawings.

第1図は本発明の実施例の一例を表わ丁ものであり、放
熱板2に絶縁層又はセラミックス板3が積層されて導体
回路4が設けられている。そして導体回路4には半導体
装置5及び抵抗体6等が塔載されており、前記導体回路
4の少なくとも縁部分には絶縁物11が被覆てれてbる
。さらに第2図は放熱板2に放熱フィン1が接合され、
半導体装置5等は樹脂封止材9により封止された本発明
の実施例の一例を表わすものである。また前記の半導体
装置は、第5図に示す中空となるパッケージ8で封止す
る方法でもよい。
FIG. 1 shows an example of an embodiment of the present invention, in which an insulating layer or a ceramic plate 3 is laminated on a heat sink 2, and a conductor circuit 4 is provided. A semiconductor device 5, a resistor 6, etc. are mounted on the conductor circuit 4, and at least an edge portion of the conductor circuit 4 is covered with an insulator 11. Furthermore, in FIG. 2, the radiation fin 1 is joined to the radiation plate 2,
The semiconductor device 5 and the like represent an example of an embodiment of the present invention in which the semiconductor device 5 and the like are sealed with a resin sealing material 9. Further, the semiconductor device described above may be sealed with a hollow package 8 as shown in FIG.

本発明に用いる放熱板2の材質としては、銅、鉄、ニッ
ケル、アルミニウム、真ちゅう及びステンレス鋼等の板
である。また絶縁層又はセラミックス板3としては、エ
ポキシ樹脂、ポリイミド樹脂及びこれら樹脂に無機充て
ん剤を充てんしたり、ガラス繊維等の繊維で補強した絶
縁層、アルミナ、シリコーンカーバイド、窒化アルミニ
ウム、ベリリア等のセラミックス板が使用される。
The material of the heat sink 2 used in the present invention is copper, iron, nickel, aluminum, brass, stainless steel, or the like. The insulating layer or ceramic plate 3 may be made of epoxy resin, polyimide resin, an insulating layer made of these resins filled with an inorganic filler, or reinforced with fibers such as glass fiber, or ceramics such as alumina, silicone carbide, aluminum nitride, beryllia, etc. board is used.

本発明に用Aられる導体回路4は、銅、鉄、ニッケル、
真ちゅう等の金属箔及びこれらの会合又は異種金属が積
層されたものであってもよい。嘔うに銅箔の場合にはワ
イヤーボンディング全容易にするため、あらかじめ金め
つき又はニッケルめっきを施しておいてもよい。
The conductor circuit 4 used in the present invention includes copper, iron, nickel,
It may be a metal foil such as brass, an association thereof, or a laminate of different metals. In particular, in the case of copper foil, it may be plated with gold or nickel in advance to facilitate wire bonding.

次に本発明に用Aられる絶縁物11は、導体回路4に付
着した気泡12を除去するため導体回路4に密着性に富
んだものが好lしく、例えばエポキシ樹脂、ポリエステ
ル樹脂又はこれら樹脂と重縮合可能な異種樹脂、さらに
シリカ、溶融シリカ、アルミナ等の熱伝導性にすぐれた
無機充てん剤及び異種耐熱樹脂粉末を含有させたもので
もよい。
Next, the insulator 11 used in the present invention is preferably one that has good adhesion to the conductor circuit 4 in order to remove air bubbles 12 attached to the conductor circuit 4, and is made of, for example, epoxy resin, polyester resin, or these resins. It may contain a different resin capable of polycondensation, an inorganic filler with excellent thermal conductivity such as silica, fused silica, alumina, and a different heat-resistant resin powder.

そして絶縁物11は導体回路4に厚さ3μm〜i、oo
oμmで被覆するのが好ましく、厚さが6μm未満では
気泡全十分に除去することができず、耐電圧の低下を防
止することができない。さらに被覆の厚さu i、o 
o oμmfc越えても何んら差し支えないが、耐電圧
低下の防止にはIU効来がなく、塗工等の処理王台から
i、oooμmが好ましい厚さである。
The insulator 11 is applied to the conductor circuit 4 with a thickness of 3 μm to i, oo.
It is preferable to cover with a thickness of 0 μm. If the thickness is less than 6 μm, all the air bubbles cannot be sufficiently removed and a decrease in withstand voltage cannot be prevented. Furthermore, the coating thickness u i, o
Although there is no problem even if the thickness exceeds fc, IU is not effective in preventing a drop in withstand voltage, and the preferred thickness is i, ooo μm from the standpoint of processing such as coating.

次に絶縁物11は導体回路4の全面に被覆し、半導体装
置5等を塔載する部分を剥離して使用することができる
が、あらかじめ半導体装置5等を塔載する位置が決めら
れていれば、その場所t−あらかじめ露出するようにす
ることも可能である。
Next, the insulator 11 can be used by covering the entire surface of the conductor circuit 4 and peeling off the part on which the semiconductor device 5 etc. will be mounted, but the position where the semiconductor device 5 etc. will be mounted must be determined in advance. For example, it is also possible to expose the location t- beforehand.

また導体回路4に半導体装置5等を塔載した後、残9の
部分に絶縁物11に被覆する方法であってもよい。そし
て絶縁物11は第3図に示すとおり導体回路4の表面層
から側面そして底面葦で連続して被覆することが耐電圧
の低下を防止する上で効果があり、さらに表面層は(a
)の幅が50丸以上であることが耐電圧低下の防止で効
果がある。
Alternatively, after the semiconductor device 5 and the like are mounted on the conductor circuit 4, the remaining 9 portions may be covered with the insulator 11. As shown in FIG. 3, it is effective to cover the insulator 11 continuously from the surface layer of the conductor circuit 4 to the side and bottom reeds to prevent a drop in withstand voltage.
) is 50 circles or more in width, which is effective in preventing a drop in withstand voltage.

また側面から底面にかけては(1))の幅が100μm
以上好1しくに500μm以上が耐電圧低下の防止に効
果がある。絶縁物11の導体回路4への被覆する方法と
しては、スクリーン印刷、吹き付は法が好葦しく、その
他回路基板全損傷しないものであれば、どのような被覆
方法でも差し支えなh0本発明の回路基板を製造する具
体的な方法としては、前記の絶縁層又はセラミックス板
が接金された放熱板に接着剤を介して前記の金属箔から
なる導体回路を形成させる。次に導体回路の半導体装置
(トランジスター ダイオード等)、抵抗体(チップ抵
抗、チップコンデンサー等)及び端子等が塔載予定され
る部分を除^て、導体回路表面層の全面又は表面層にか
けての周縁部分から側面、絶縁層又はセラミックス板の
面に連続するように絶縁物を例えばスクリーン印刷又は
吹き付けにて塗布する。次いで絶縁物が硬化した後導体
回路の露出部分に半導体装置等の部品を塔載する。そし
て樹脂封止材又は中空パッケージで、導体回路面を密封
し、さらに必要に応じて放熱板は底面に放熱フィンを取
り付ける。
Also, from the side to the bottom, the width of (1)) is 100 μm.
A thickness of preferably 500 μm or more is effective in preventing a drop in withstand voltage. As a method of coating the conductor circuit 4 with the insulator 11, screen printing and spraying are preferred, and any other coating method may be used as long as it does not damage the entire circuit board. A specific method for manufacturing a circuit board is to form a conductor circuit made of the metal foil on a heat sink to which the insulating layer or ceramic plate is welded via an adhesive. Next, remove the entire surface of the conductor circuit surface layer or the periphery of the surface layer, excluding the areas where semiconductor devices (transistors, diodes, etc.), resistors (chip resistors, chip capacitors, etc.), terminals, etc. of the conductor circuit are planned to be mounted. The insulating material is applied continuously from the part to the side surface, the insulating layer, or the surface of the ceramic plate by, for example, screen printing or spraying. After the insulator is cured, a component such as a semiconductor device is mounted on the exposed portion of the conductor circuit. Then, the conductor circuit surface is sealed with a resin sealant or a hollow package, and if necessary, a heat dissipation fin is attached to the bottom of the heat dissipation plate.

そして本発明の牛導体塔載用回路基板は、広義でいうパ
ワー半導体装置塔載モジュール用であり混成集積用回路
基板([C)も含まれる。
The circuit board for mounting on a conductor tower of the present invention is for a power semiconductor device tower mounting module in a broad sense, and also includes a circuit board for hybrid integration ([C)].

また導体回路周縁部分への樹脂又は無機充てん剤含有樹
脂絶縁物の塗布は、導体回路の周縁部分全体に被覆する
ことが望ましいが、半導体装置、抵抗体、リード端子及
び基板の大きさの部会上導体回路の周縁部分の一部が露
出することがあるが、耐電圧低下の程度は小さく効果に
はさほど影響を与えるものでない。さらに本発明に用い
る絶縁物11は、第1図及び第2図に示すとおり半導体
装置5等の塔載部品に密着するよりに、またその他の全
ての導体回路4を被覆してもよ^。
Furthermore, when applying resin or resin insulating material containing an inorganic filler to the periphery of a conductor circuit, it is desirable to cover the entire periphery of the conductor circuit, but depending on the size of the semiconductor device, resistor, lead terminal, and board. Although a portion of the periphery of the conductor circuit may be exposed, the degree of reduction in withstand voltage is small and does not significantly affect the effect. Furthermore, the insulator 11 used in the present invention may cover all other conductive circuits 4 instead of being in close contact with mounted components such as the semiconductor device 5 as shown in FIGS. 1 and 2.

このように本発明は導体回路の少なくとも周縁部分に樹
脂状の絶縁換金形成による気泡を除去することと、各構
成材料の比誘電率の相違すなわちセラミックス基板又は
金属ベース基板の絶縁層の比誘電率は通常7.0〜4.
0稲度であるが、これを封止する樹脂は通常5.0、そ
して導体回路の周縁部分に塗布する樹脂又は無機充てん
剤含有樹脂絶縁物の比誘電率は、通常4.0〜4.5程
度であり、これら3稲の比誘電率が′異なることによっ
て電界集中の緩和を導くことができ耐電圧の低下を防止
することができる。
As described above, the present invention eliminates air bubbles by forming a resin-like insulation in at least the peripheral portion of a conductor circuit, and also eliminates the difference in relative permittivity of each constituent material, that is, the relative permittivity of the insulating layer of a ceramic substrate or a metal base substrate. is usually 7.0 to 4.
0 degrees Celsius, but the resin used to seal it usually has a dielectric constant of 5.0, and the dielectric constant of the resin or inorganic filler-containing resin insulator applied to the peripheral portion of the conductor circuit is usually 4.0 to 4.0 degrees. The dielectric constants of these three types are different, which leads to relaxation of electric field concentration and prevents a decrease in withstand voltage.

(実施例) 実施例1 厚さ100μmのアルミナ基板に銀ロクペーストによジ
厚さ1(175μmの銅箔を接金して導体回路を形成し
た。次贋で導体回路の表面層縁部分より中心に向って1
.11幅、側面及びアルミナ面2趨幅にわたって連続的
に極低粘度液状エポキシ樹脂を5μmの厚さとなるよう
にスプレーした。エポキシ樹脂を加熱・硬化させた後に
導体回路の露出部分に半導体装置等の部品を塔載し外装
ケースを接着した後、S10□含有エポキシ樹脂を注入
し封止した。
(Example) Example 1 A conductor circuit was formed by bonding copper foil with a thickness of 1 (175 μm) to a 100 μm thick alumina substrate using silver paste. 1 towards the center
.. An extremely low viscosity liquid epoxy resin was continuously sprayed to a thickness of 5 μm over the width of No. 11, the side surface, and the two widths of the alumina surface. After heating and curing the epoxy resin, parts such as a semiconductor device were mounted on the exposed portion of the conductor circuit, and an outer case was adhered thereto, followed by injection of an epoxy resin containing S10□ for sealing.

次に導体回路と放熱板との間にA C4,Q kv/室
温にて電圧をかけ寿命ナス11−行った。絶縁破壊平均
寿命は146時間であった。また比較として導体回路に
樹脂塗布しないもの全測定したところ平均寿命は47時
間であった。
Next, a voltage of AC4, Q kv/at room temperature was applied between the conductive circuit and the heat sink to reduce the lifespan. The average dielectric breakdown life was 146 hours. For comparison, we measured all the conductor circuits without resin coating, and found that the average lifespan was 47 hours.

実施例2 厚さ80μmの絶縁層を有する6B厚のアルミニウム基
板に無機充てん剤高充てんエポキシ樹脂全接着剤として
厚さ85μmの銅箔及び厚さ40μ出のアルミニウム箔
の複会箔を接着し、エツチング処理して導体回路全形成
した。次いで導体回路面半導体装置等の導体回路の表面
層R部分より中心に向って200μm幅、側面、絶縁層
3H幅にわたって連続的にSiO□含有エポキシ/メラ
ミン樹脂t−15μmの厚さでスクリーン印刷した。
Example 2 A composite foil of an 85 μm thick copper foil and a 40 μm thick aluminum foil was bonded to a 6B thick aluminum substrate having an 80 μm thick insulating layer as an inorganic filler and highly filled epoxy resin adhesive. The entire conductor circuit was formed by etching. Next, a 200 μm width from the surface layer R portion of the conductor circuit of the conductor circuit surface semiconductor device, etc. toward the center, the side surfaces, and the insulating layer 3H width were screen printed with a SiO□-containing epoxy/melamine resin t-15 μm thick. .

次に樹脂コート部分が硬化後半導体装置、抵抗体、端子
等を塔載した後に外装ケースを接着し、810□含有エ
ポキシ樹脂金注入し封止した。出来上った回路基板を1
25℃のオープン内でAC片波800vピークで寿命試
験を行ったところ平均寿命27時間であった。また比較
として導体回路に樹脂塗布しないものを測定したところ
平均寿命は8時間であった。
Next, after the resin coated portion was cured, a semiconductor device, a resistor, a terminal, etc. were mounted thereon, and then an outer case was adhered, and an epoxy resin containing 810□ was injected with gold and sealed. The completed circuit board is 1
When a lifespan test was conducted in an open room at 25°C with an AC single wave of 800V peak, the average lifespan was 27 hours. For comparison, measurements were taken of a conductor circuit without resin coating, and the average lifespan was 8 hours.

実施例3 実施例20回路基板でSiO□含有エポキシ樹脂注入封
止の代わりに中空パック−22行った以外は、実施例2
と同様の操作を行った結果平均寿命は15時間であり、
また半田レジストを塗布しない場合は、4時間であった
Example 3 Example 20 Same as Example 2 except that hollow pack-22 was used instead of SiO□-containing epoxy resin injection sealing for the circuit board.
As a result of performing the same operation as above, the average lifespan was 15 hours,
In addition, when no solder resist was applied, the time was 4 hours.

(発明の効果) 以上のとおり本発明は、回路基板全作成するにあたって
、導体回路の周縁部分全樹脂状絶縁物で被覆して気泡付
着全防止すると共に異なる比誘電率の組仕せによる回路
基板を用いることにより、電界集中全緩和し、耐電圧の
低下を防止して回路基板としての寿命を延ばす効果を有
するものである。
(Effects of the Invention) As described above, the present invention provides a circuit board in which the entire periphery of the conductor circuit is coated with a resin-like insulator to completely prevent the adhesion of air bubbles, and the circuit board is assembled with different dielectric constants. By using this, the electric field concentration is completely relaxed, the withstand voltage is prevented from decreasing, and the life of the circuit board is extended.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の回路基板、第2図は樹脂封止材で封止
した本発明の回路基板のそれぞれ側面断面図を表わす。 また第5図は、本発明の回路基板の拡大側面断面図全表
わす。第4図は従来の回路基板の側面断面図でらり、第
5図は導体回路に気泡が付着した状態を表わす部分側面
断面図t−表わす。第6図は導体回路部分全露出させ、
その他を半田レジストで被覆した従来例の平面図を表わ
す。 符号 1・・放熱フィン        1・・・端子2・・
・放熱板          8・・・パッケージ3・
・・絶縁層又はセラミックス板 9・・・樹脂封止材4
・・・導体回路        10・・・ワイヤー5
・・・半導体装#t       11・・・絶縁物6
・・・抵抗体         12・・・気泡13・
・・半田レジスト
FIG. 1 shows a side sectional view of the circuit board of the present invention, and FIG. 2 shows a side sectional view of the circuit board of the present invention sealed with a resin sealing material. FIG. 5 is an enlarged side cross-sectional view of the circuit board of the present invention. FIG. 4 is a side sectional view of a conventional circuit board, and FIG. 5 is a partial side sectional view showing a state in which air bubbles are attached to a conductor circuit. Figure 6 shows the conductor circuit part completely exposed.
A plan view of a conventional example in which other parts are covered with solder resist. Code 1...Radiation fin 1...Terminal 2...
・Heat sink 8...Package 3・
...Insulating layer or ceramic plate 9...Resin sealing material 4
...Conductor circuit 10...Wire 5
... Semiconductor device #t 11 ... Insulator 6
...Resistor 12...Bubble 13.
・Solder resist

Claims (3)

【特許請求の範囲】[Claims] 1.導体回路を設けた絶縁基板の前記導体回路の少なく
とも周縁部分に樹脂又は無機充てん剤含有樹脂絶縁物を
被覆してなることを特徴とする半導体塔載用回路基板。
1. 1. A circuit board for mounting a semiconductor, comprising an insulating substrate provided with a conductor circuit, and at least a peripheral portion of the conductor circuit is coated with a resin or an inorganic filler-containing resin insulator.
2.導体回路を設けた絶縁基板の前記導体回路の少なく
とも周縁部分に樹脂又は無機充てん剤含有樹脂絶縁物を
被覆された前記導体回路露出部に半導体装置等を塔載し
てなることを特徴とする半導体塔載用回路基板。
2. A semiconductor comprising an insulating substrate provided with a conductor circuit, at least a peripheral portion of the conductor circuit being coated with a resin or an inorganic filler-containing resin insulator, and a semiconductor device or the like being mounted on the exposed portion of the conductor circuit. Tower-mounted circuit board.
3.絶縁基板上に導体回路を形成し、該導体回路の少な
くとも周縁部分を樹脂又は無機充てん剤含有樹脂絶縁物
で被覆した後、前記導体回路の露出部に半導体装置を塔
載することを特徴とする半導体塔載用回路基板の製造方
法。
3. A conductor circuit is formed on an insulating substrate, at least a peripheral portion of the conductor circuit is coated with a resin or an inorganic filler-containing resin insulator, and then a semiconductor device is mounted on the exposed portion of the conductor circuit. A method for manufacturing a circuit board for mounting a semiconductor tower.
JP24503689A 1989-09-22 1989-09-22 Semiconductor tower mounting circuit board and method of manufacturing the same Expired - Fee Related JP2726515B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24503689A JP2726515B2 (en) 1989-09-22 1989-09-22 Semiconductor tower mounting circuit board and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24503689A JP2726515B2 (en) 1989-09-22 1989-09-22 Semiconductor tower mounting circuit board and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH03108362A true JPH03108362A (en) 1991-05-08
JP2726515B2 JP2726515B2 (en) 1998-03-11

Family

ID=17127630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24503689A Expired - Fee Related JP2726515B2 (en) 1989-09-22 1989-09-22 Semiconductor tower mounting circuit board and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2726515B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04268786A (en) * 1991-02-25 1992-09-24 Matsushita Electric Works Ltd Printed wiring board
JPH07161757A (en) * 1993-12-03 1995-06-23 Fuji Dies Kk Heat piece
JP2008085169A (en) * 2006-09-28 2008-04-10 Mitsubishi Electric Corp Power semiconductor module
JP2020129589A (en) * 2019-02-07 2020-08-27 積水化学工業株式会社 Semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52151863A (en) * 1976-06-11 1977-12-16 Hitachi Ltd Method of coating integrated circuit
JPS57125542U (en) * 1981-01-30 1982-08-05
JPS59107147U (en) * 1983-01-07 1984-07-19 日本電気株式会社 semiconductor equipment
JPS6364049U (en) * 1986-10-14 1988-04-27

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52151863A (en) * 1976-06-11 1977-12-16 Hitachi Ltd Method of coating integrated circuit
JPS57125542U (en) * 1981-01-30 1982-08-05
JPS59107147U (en) * 1983-01-07 1984-07-19 日本電気株式会社 semiconductor equipment
JPS6364049U (en) * 1986-10-14 1988-04-27

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04268786A (en) * 1991-02-25 1992-09-24 Matsushita Electric Works Ltd Printed wiring board
JPH07161757A (en) * 1993-12-03 1995-06-23 Fuji Dies Kk Heat piece
JP2008085169A (en) * 2006-09-28 2008-04-10 Mitsubishi Electric Corp Power semiconductor module
JP2020129589A (en) * 2019-02-07 2020-08-27 積水化学工業株式会社 Semiconductor device

Also Published As

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