JPH0310976B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory access control method for a memory device shared by a plurality of memory access requesting devices such as processors and devices.

[Background of the invention]

A memory device that is shared by multiple processors or devices (memory access requesting devices) is connected to them via a bus, but in order to increase the efficiency of the bus, a buffer device is generally installed between the bus and the memory device. I am intervening. Memory access control in such a memory system is performed as follows.

When a memory access request is issued by a memory access requesting device, the right to use the bus is granted to one memory access requesting device on the condition that the bus and buffer device are free, and the memory access to which the right to use the bus is granted is granted. Information regarding the memory access request of the requesting device, such as the address, data, and whether it is a read or write request, is carried on the bus and stored in the buffer device. The buffer device is configured to be able to accumulate information on multiple memory access requests. One or more memory access requests stored in the buffer device are sequentially received and sent to the memory device in a priority order determined by the source of the request and whether it is a read or write request.

In such a memory access control method, when a memory access request with the highest priority (urgent memory access request) occurs, if memory access requests have already been stored in the buffer device, one of the memory access requests is There is a problem in that the acceptance of an urgent memory access request cannot be given priority over the memory access request with the highest priority, and the acceptance and execution of the urgent memory access request is delayed accordingly.

Further, as a prior art related to priority processing of memory access requests, a memory access request and addition information of the allowable waiting time of the request and the request issuing time are stacked as a set, and from among the stacked memory access requests, A memory access control method is known in which the added information is accepted in order of the smallest value and sent to the memory device (Japanese Patent Application Laid-Open No. 79354/1983).

[Purpose of the invention]

An object of the present invention is to more quickly accept an urgent memory access request from a memory access requesting device of the highest order in a memory system in which a memory device is connected to a plurality of memory access requesting devices via a bus and a buffer device. The object of the present invention is to provide a memory access control method that can handle this problem.

[Summary of the invention]

In a memory system in which a plurality of memory access requesting devices are connected to a memory device via a bus and a buffer device, when a specific memory access requesting device with the highest priority is permitted to use a bus, To suppress the operation of a memory reception circuit that receives memory access requests stored in a buffer device in priority order until information on a memory access request (urgent memory access request) from a memory access request device is stored in the buffer device. This is intended to allow urgent memory access requests to be accepted and processed with priority over previous memory access requests.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In Figure 1, 1, 2, and 3 are memory access requesting devices (processors or devices).
and is connected to the buffer device 5 via the bus 10. This buffer device 5 has an address,
It is provided with a plurality of registers 51 to 61 for storing memory access request information such as data. Buffer device 5 is connected to memory device 9 via memory bus 20 . Memory bus 20 consists of address, data and control signals necessary for memory access.

Reference numeral 4 denotes a bus acceptance circuit that selectively grants the right to use the bus 10 to the memory access requesting devices 1, 2, and 3. Memory access request devices 1, 2, 3 send bus request signals 11, 2 to bus acceptance circuit 4.
1 and 31, respectively, and when a memory access request occurs, the bus request signals 11, 21, and 3 are
Turn on 1. The bus reception circuit 4 is in a state where the empty signal 53 of the buffer device 5 is on (there is space in the registers 51 to 61 in the buffer device 5), and the bus is in an empty state (not shown) or the bus strobe line (memory access request device is not connected). When one or more of the bus request signals 11, 21, and 31 is turned on (signal line indicating that information on the bus 10 is carried) is turned off, a predetermined priority is given to the bus request signal that is turned on. One of them is accepted according to the order, and the acceptance permission signal for the memory access requesting device that has issued the accepted bus request signal among the acceptance permission signals 12, 22, and 32 is turned on. accepted by bus acceptance circuit 4, that is, bus 1
The memory access requesting device that has been given the usage right of 0 puts memory access request information on the bus 10, and the memory access request information is stored in one of the vacant registers 51 to 61 in the buffer device 5.

7 is a memory reception circuit, and a buffer device 5
Memory request signal 5 from registers 51 to 61 in
2 to 62 recognize the memory access requests stored in the registers 51 to 61, select and accept one of these memory access requests in a predetermined order, and store the information of the memory access request in the memory. The bus 20 is controlled by the reception control line 8 so as to load onto the bus 20. However, when the acceptance permission signal 32 is turned on, the operation of the memory acceptance circuit 7 is temporarily inhibited.

Next, the operation will be explained. Note that the memory access requesting device 1 is given the highest priority, and its memory access request is processed as an urgent memory access request.

For example, when memory access request devices 2 and 3 simultaneously generate memory access requests, the bus request signal 2
Suppose that 1 and 31 are turned on. In this case, bus 10
is in an empty state, and if any of the registers 51 to 61 of the buffer device 5 is empty, the bus acceptance circuit 4 accepts a bus request from one of the memory access requesting devices (for example, 2) and sends an acceptance permission signal. Turn on 22. The memory access requesting device 2 that is permitted to use the bus puts the information of the memory access request on the bus 10. This memory access request information is stored in a register 51 in the buffer device 5.
It is stored in one of the 61 vacant spaces. The memory acceptance circuit 7 accepts one of the memory access requests stored in the buffer device 5, and sends the information of the memory access request onto the memory bus 20 to the memory device 9 to perform a memory access operation. If the memory access is a read, the read data is transferred to the memory bus 20 and the buffer device 5.
The data is then transferred via the bus 10 to the memory access requesting device that issued the request. When the memory access is a write, the write data stored in the buffer device 5 is written to the memory device 9. When the memory access operation is completed, the buffer device 5
The access request state within is reset.

The above is normal memory access operation other than express memory access. Next, the urgent memory access request operation will be explained.

When an urgent memory access request is generated in the memory access requesting device 1 and the bus request signal 11 is turned on, even if other bus request signals 21 and 31 are turned on at the same time, the request from the memory access requesting device 1 is accepted with priority, The acceptance permission signal 12 is turned on. When the acceptance permission signal 12 is turned on, the operation of the memory acceptance circuit 7 is inhibited, and even if there is a memory access request waiting to be accepted in the buffer device 5 at that time, the acceptance thereof is suspended.

When the information of the express memory access request is stored in the buffer device 5 via the bus 10 and the bus acceptance circuit 4 turns off the acceptance permission signal 12, the memory acceptance circuit 7 is released from the inhibition and the request in the buffer device 5 is no longer accepted. I do. Since the urgent memory access request is given the highest priority, even if there are other memory access requests in the buffer device 5, the urgent memory access request is accepted with priority over them.

Although one embodiment has been described above, the present invention is not limited thereto, and it goes without saying that it can be implemented with various modifications.

〔Effect of the invention〕

As described above, according to the present invention, since an urgent memory access request is accepted with priority over a preceding memory access request, an effect can be obtained in that the urgent memory access request can be processed more quickly than before.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1, 2, 3... memory access request device, 4...
...Bus reception circuit, 5...Buffer device, 7...
Memory reception circuit, 9...Memory device, 10...
bus, 11, 21, 31... bus request signal, 12,
22, 32...Acceptance permission signal, 20...Memory bus, 51-61...Register, 52-62...
Memory request signal.

Claims (1)

[Claims] 1. A buffer device connected to a plurality of memory access requesting devices via a bus, a memory device connected to the buffering device, and bus use requests from the memory access requesting devices are received and accepted in order of priority. A bus reception circuit that transfers memory access request information of one memory access requesting device to the buffer device via the bus, and selecting memory access request information stored in the buffer device according to priority order and transmitting the memory access request information to the memory device. and a memory acceptance circuit that causes the bus to be used by the specific memory access requesting device, and when the bus acceptance circuit accepts a bus usage request from a specific memory access requesting device with the highest priority among the memory access requesting devices, 1. A memory access control system, comprising: inhibiting operation of said memory reception circuit until said memory access request information is stored in said buffer device.