JPH03110558U - - Google Patents

Info

Publication number
JPH03110558U
JPH03110558U JP1859690U JP1859690U JPH03110558U JP H03110558 U JPH03110558 U JP H03110558U JP 1859690 U JP1859690 U JP 1859690U JP 1859690 U JP1859690 U JP 1859690U JP H03110558 U JPH03110558 U JP H03110558U
Authority
JP
Japan
Prior art keywords
operational amplifier
output terminal
input terminal
terminal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1859690U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1859690U priority Critical patent/JPH03110558U/ja
Publication of JPH03110558U publication Critical patent/JPH03110558U/ja
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す回路図、第2
図は従来の積分回路図、第3図は従来の比例積分
回路図である。 OP……演算増幅器、R……入力抵抗、R
……帰還抵抗、C……帰還コンデンサ、D1,
……ダイオード、SW……FETスイツチ
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a conventional integral circuit diagram, and FIG. 3 is a conventional proportional integral circuit diagram. OP...Operation amplifier, R i ...Input resistance, R f
...Feedback resistance, C f ...Feedback capacitor, D 1,
D2 ...Diode, SWr ...FET switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 信号入力端子と演算増幅器の入力端子間に接続
された入力回路と、前記演算増幅器の反転入力端
子と出力端子間に接続されたリセツト用アナログ
スイツチと、前記演算増幅器の出力端子と信号出
力端子間に接続されたダイオードと、前記演算増
幅器の入力端子と信号出力端子間に接続された帰
還回路とを備えたことを特徴とする演算回路のリ
セツト回路。
an input circuit connected between a signal input terminal and an input terminal of an operational amplifier; a reset analog switch connected between an inverting input terminal and an output terminal of the operational amplifier; and an output terminal of the operational amplifier and a signal output terminal. 1. A reset circuit for an arithmetic circuit, comprising: a diode connected to the operational amplifier; and a feedback circuit connected between the input terminal and the signal output terminal of the operational amplifier.
JP1859690U 1990-02-26 1990-02-26 Pending JPH03110558U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1859690U JPH03110558U (en) 1990-02-26 1990-02-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1859690U JPH03110558U (en) 1990-02-26 1990-02-26

Publications (1)

Publication Number Publication Date
JPH03110558U true JPH03110558U (en) 1991-11-13

Family

ID=31521750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1859690U Pending JPH03110558U (en) 1990-02-26 1990-02-26

Country Status (1)

Country Link
JP (1) JPH03110558U (en)

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