JPH03110647A - Memory capacity extending system for microcomputer system - Google Patents

Abstract

PURPOSE:To increase the memory capacity by inserting a register and a logic circuit between the address output of a CPU and the address input of a memory device. CONSTITUTION:Memory devices 4 to 6 are provided beyond a maximum memory capacity determined by the number of address terminals of a CPU 1. The CPU 1 writes mapping information of the memory in a register 2, and a logic part 3 receives the address input of upper four bits from the CPU 1 and outputs the enable output and data of the address output of upper four bits to memories 4 to 6 based on the data input from the register 2. The enable output is outputted to the memory device determined by the address input of upper four bits and the mapping data output, and the address output is outputted by combination of the address input of upper four bits and mapping data. Thus, the memory capacity is increased.

Description

[Detailed description of the invention] [Industrial application field]

The present invention is applicable to a CP where the address bus is, for example, only 16 bits.
This invention relates to a memory capacity expansion method in the U system.

[Conventional technology]

Conventionally, when the address output of a CPU and the address input of a memory device are directly connected, the memory capacity is only as large as the address output of the CPU. In other words, if the address was 16 bits, it was not possible to have a memory larger than 64 kilobytes.

[Problem to be solved by the invention]

If the conventional CPU address was 16 bits, it was not possible to have a memory of more than 64 kilobytes. Therefore, it was not possible to increase the amount of data handled by the CPU beyond 64 kilobytes at most.

[Means to solve the problem 1. One register and logic circuit such as FROM
Insert between the address output of the memory and the address input and enable input of the memory. The output of the data written in the register and the address output from the CPU are input to a logic circuit such as FROM, and the output is connected to the upper address and enable input of the added memory device. [Operation] The memory load increased by the upper address of the CPU output and the data output written to the register is divided.

【Example】

An embodiment of the present invention will be described below with reference to FIG. The CPU 1 writes memory mapping information, which will be described later, to the register 2 via data input. The register 2 outputs the fetched data to the logic section 3. The logic unit 3 receives the upper 4 bits of address input from the CPUI, and outputs the enable output and the upper 4 bits of address output data to the memory 4.5.6 based on the data input from the register 2. The addresses of the lower bits of the CPUI are directly connected to the address inputs of the memories 4, 5.6. FIG. 2 shows the memory map of the embodiment, with address 000
0 to 7 FFF is memory 1.8000 to FFF
Memory 5 is used up to F. However, from 8000 to B
The memory 6 is also used redundantly up to FFF. This area is made up of banks 0 to 5, and the CPU
A combination determined in advance by the data output from I (
For example, a combination of bank 0 and bank 3, or a combination of bank 4 and bank l, etc.) is specified. As is clear from FIG. 2, the memory capacity can be increased by the amount of memory 6. The enable output of the logic section 3 outputs an enable signal to the memory device determined by the address input of the upper 4 bits of the CPUI and the mapping data (code) output. Also, the address output of the logic section 3 is
It is output by a combination of the upper 4 bits of address input from I and mapping data (code).

【Effect of the invention】

As described above, according to the present invention, by inserting a register and a logic circuit between the address output of the CPU and the address input of the memory device, 1. 5 times 96
It was possible to increase the memory capacity to kilobytes. Further, if this method is used, it is possible to increase the memory capacity even more, although it was 1.5 times as large in the case of the embodiment.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a memory capacity expansion method according to the present invention, and FIG. 2 is a diagram showing memory allocation in the embodiment. i-cpu, 2--register, 3--logic section, 4-6- memory.

Claims (1)

[Claims] A memory device is provided that exceeds the maximum memory capacity determined by the number of address terminals of the CPU, and an enable signal and upper address signal to this memory device are output from a logic circuit based on memory mapping data and upper address signal from the CPU. A memory capacity expansion method for microcomputer systems.