JPH0311143B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission line adapter using a character buffer method.

In general, as a transmission data control method applied to data communication systems, a method is adopted in which the communication control unit LC receives transmission data from the data processing unit PU, decomposes it into bit serial data in the line adapter LA, and then sends it out to the line. has been done.
This system is schematically shown in Figure 1. In this system, when the communication control device LC receives a special transmission character, it may temporarily take a long time to process the transmission for that character. For example, adding DLE when receiving a DLE code in transparent transmission,
Another example is the generation of a control field when an address character is received in high data link control (HDLC) mode. Even in such cases, in order to be able to transmit the next character in time for the transmission speed of the line, it is possible to shorten the character processing time of the communication control device LC, or to install multiple character buffers in the line adapter. A type with a first-in/first-out shift memory is considered.

The method of reducing character processing time has the disadvantage that if the transmission speed of the line is high, it becomes difficult to perform all character processing in the communication control device within one character transmission time. The method of providing a network adapter has the disadvantage that the number of circuits for the line adapter increases. To that end, we are currently working on First Inn.
A method of providing a first-out shift memory is adopted. For example, JP-A-58-19062 describes a buffer register that temporarily stores transmission characters from a communication control section, a shift register that decomposes transmission characters into bit serials, and a system that controls the operations of these various registers and A first-in/first-out shift memory is provided after the shift register of the line adapter, which has a transmission control circuit that controls input/output operations with the control unit, and the transmission side control circuit transmits data transmitted from the communication control unit. By adopting a method of sequentially storing data in the first-in/first-out shift memory and transmitting the contents of the first-in/first-out shift memory to the line at the bit transmission rate of the line, the character processing time of the communication control unit can be reduced. It has been shown that temporary peak values can be alleviated (the inventor is the same as the inventor of the present application). However, even if a first-in/first-out shift memory is used, if the difference between the bit transmission speed of the data sent to the line and the speed of the data transferred from the shift register to the first-in/first-out shift memory is insufficient, Conventionally, when the transmit character buffer is empty, the transmit data bits are input from the transmit shift register to the first-in/first-out shift memory until the transmit character is set from the communication control device to the transmit character buffer. Since this is prohibited, there is a drawback that the transmission data will be lost in the first-in/first-out shift memory.

An object of the present invention is to enable the first-in/first-out shift memory to maintain a high speed even when the difference between the bit transmission speed of the transmission data to the line and the speed at which the transmission data bits are stored in the first-in/first-out shift memory is insufficient. To provide a communication control line adapter capable of high-speed processing without becoming empty.

According to the present invention, there is provided a buffer register that temporarily stores transmission characters from a communication control device, a shift register that decomposes the transmission characters obtained from the buffer register into bit serials, and a first input register that stores the output of the shift register.・
a first-out shift memory; and a transmission character is given from the communication control device to the buffer register, and the first-in/first-out shift memory is sequentially stored in the first-in/first-out shift memory via the shift register. sending the contents to the line and either the first-in/first-out shift memory becomes "full" or the contents of the buffer register are transferred to the shift register;
After the buffer register becomes "empty" and the contents of the shift register are transferred to the first-in/first-out shift memory by the required number of bits minus one bit, the data is sent to the first-in/first-out shift memory. If the transfer of data bits is temporarily stopped and the first-in/first-out shift memory becomes "empty", or if the transmit character is set in the buffer register, the first-in/first-out shift memory is A line adapter is obtained having a transmission control circuit for controlling the transfer of transmission data bits to a shift memory.

Next, examples of the line adapter according to the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing the structure of an embodiment according to the present invention. Further, FIG. 4 is a time chart for explaining the operation of this embodiment. In this example, 8 bits/character is used. In FIG. 2, the transmission character from the communication control unit LC is received by the transmission buffer register 1. In FIG. Referring to FIG. 4, when the transmit buffer "full" signal is "0", the LC sends it to the transmit buffer register 1. Since the transmit character is set in the transmit buffer register 1, the transmit buffer "full" signal becomes "1". The transmission character of transmission buffer register 1 is shift register 2.
Referring to FIG. 4, the transmit signal character of the transmit buffer register 1 is sent to the shift register 2 by the shift register set timing signal. After being decomposed into bit serials,
It is sent to the first-in/first-out shift memory 3. Regarding FIG. 4, the data is sequentially input to the first-in/first-out shift memory by the character decomposition timing signal (FIFO input timing). That is, the third
As seen in the specific example of the first-in/first-out shift memory in the figure, the transmission data stored in the first stage shift memory 3-1 waits for the next stage shift memory 3-2 to become empty. be transferred there. Thereafter, this transmission data is moved toward the n-th stage shift memory 3-n by a similar operation.

On the other hand, the contents of the first-in/first-out shift memory 3 are transmitted to the line under the control of the transmission control circuit 4 at a timing synchronized with the bit transmission rate of the line. In FIG. 4, output data is output from the first-in/first-out shift memory as (line) transmission data depending on the transmission timing. Normally, the shift speed of the first-in/first-out shift memories is faster than the bit transmission speed of the line, so transmission data is sequentially stored in these shift memories, and eventually there may be no empty state in the shift memories.
Referring to FIG. 4, the first-in/first-out shift memory "full" signal is in the state of "1". In such a case, the transmission control circuit 4 detects this state and prohibits the transfer of transmission data from the shift register 2 to the first-in/first-out shift memory 3 until the register becomes empty. Further, when the first-in/first-out shift memory 3 is empty and the transmission buffer register 1 is filled, the contents of the shift register 2 are transferred to the first-in/first-out shift memory 3. In Fig. 4, the Dn-7th bit data of the shift register is first-ined at the character decomposition timing.
Enter into first out shift memory. With this, the first-in/first-out shift memory becomes full and the first-in/first-out "full" signal becomes "1". Next, when the data in the first-in/first-out shift memory is read at the transmission timing, the first-in/first-out shift memory becomes full.
The first out “full” signal becomes “0”. Similar operations are performed thereafter. Immediately after this, when the shift register 2 detects the completion of sending one character's worth of transmission data to the first-in/first-out shift register 3, the buffer register 1
The contents of are transferred to shift register 2, and the process continues until the next transmission character is set from communication control device LC.
The transmission control circuit 4 displays that the buffer register 1 is "empty". In FIG. 4, the transmission buffer "full" signal is in the state of "0".
The transmission control circuit 4 prohibits the input of transmission data bits from the shift register 2 to the first-in/first-out shift memory 3 when the buffer register 1 is "empty" and after the required number of bits minus one bit. In FIG. 4, this is the section.

To explain the reason why the input of transmission data bits to the first-in/first-out shift memory 3 is prohibited, for example, if the bit transmission speed of the line is
The transmission speed is 48kbps, the speed at which transmission data bits are transferred from shift register 2 to first-in/first-out shift memory 3 is 64kbps, the required number of bits is 8 bits, and buffer register 1 is "empty".
Assuming that the time required for the communication control unit LC to set the transmission character in buffer register 1 is 100 μS, the conventional method would have a transmission speed of 48 kbps.
1 character time approximately 166.4μS, 64kbps at the speed of
At the speed of , it takes about 124.8μS for one character.
As a result, the buffer register 1 becomes "empty", the communication control device LC sets the transmit character, and the transmit character currently set in the shift register 2 is moved to the first-in/first-out shift memory 3. The time it takes for the communication controller to set the transmit character in the transmit buffer register is approximately equal to the time required for one character at a speed of 64 kbps.
This is 224.8μS, which exceeds the time for one character (approximately 166.4μS) at a speed of 48kbps. This is because due to the existence of the first-in/first-out shift memory, data cannot be accumulated in the first-in/first-out shift memory even though the speed of input data is faster than the speed of output. This means that not only can temporary peaks not be saved, but even under normal conditions, transmission cannot be done at the bit rate of the line. In other words, the time for one character (166.4 μs) output from the first-in/first-out shift memory 3 to the line is
Since the time for one character input from the shift register 2 to the first-in/first-out shift memory 3 (100 μS + 124.8 μs = 224.8 μs) is long, the first-in/first-out shift memory 3
This means that the data sent to the line will be lost. On the other hand, according _to the method of the present invention, as shown in FIG _{. ,1} ,
_The remaining 1 bit D _{o +1,7 is} transferred from the communication control device LC to the next one. This is done when the data D _o+2 to be transmitted is sent to the transmission buffer register 1, so the time required for the transfer is approximately
15.6μS, which is the time for one character
Less than 166.8μS. Therefore, even if the transfer of transmission data bits from the shift register to the first-in/first-out shift memory is temporarily prohibited, the drawbacks of the prior art do not occur.

In addition, due to special character processing by the communication control device, the sending of the transmission character from the communication control device may be delayed even if the required number of bits minus 1 bit has passed since the buffer register becomes “empty” temporarily. The transmission data stored in the first-in/first-out shift register is correctly transmitted on the line. Here, the reason why the elapsed time after the buffer register becomes empty is set to the required number of bits minus 1 bit is that the timing for transferring the transmission character from the buffer register to the shift register is automatically determined by the required number of bits. In the past, the buffer register changed from "full" to "empty".
The time it takes to
This is to change what was previously 124.8 μS to 1 bit (15.6 μS in the above example).

In addition, in the above embodiment, first-in
When the first-out shift memory is "empty" and the shift register and buffer register are "empty", the transmission control circuit notifies the communication control device of the detection of an underrun error. The bit capacity of the first-in/first-out shift memory to be used may be appropriately determined in relation to the difference between the bit transmission speed of the line and the processing speed of the communication control device.

As is clear from the above explanation, according to the present invention, even when the difference between the bit transmission rate of data transmitted to the line and the data rate stored in the first-in/first-out shift memory is not sufficient, Even under normal circumstances, the first-in/first-out shift memory will not become empty, and the circuit configuration will be simpler, which will greatly contribute to the high-speed transmission of data and the economical efficiency of the device. .

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an outline of a general transmission data control method applied to a conventional data communication system, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. first in
FIG. 4 is a block diagram showing an example of the configuration of a first-out shift memory, and a time chart for explaining the operation of the embodiment shown in FIG. 2. In each figure, 1 is a buffer register for transmitting characters, 2 is a shift register for decomposing transmitting characters, 3 is a first-in/first-out shift memory, and 3-1 to 3-n are first-in/first-out shift registers.
Each shift memory stage of the first-out shift memory, 4 is a transmission control circuit, PU is a data processing device,
LC is a communication control device and LA is a circuit adapter.

Claims (1)

[Claims] 1. A buffer register that temporarily stores the transmission characters from the communication control device, a shift register that decomposes the transmission characters obtained from the buffer register into bit serial, and a first-in/first-out shift that stores the output of the shift register. A transmission character is provided from the memory and the communication control device to the buffer register, and the first-in character is provided via the shift register.
The contents of the first-in/first-out shift memory are sequentially stored in the first-out shift memory and sent to the line until the first-in/first-out shift memory becomes "full" or the buffer register is filled. After the contents are transferred to the shift register, the buffer register becomes "empty", and the contents of the shift register are transferred to the first-in/first-out shift memory by the required number of bits minus one bit, the first-in - temporarily suspending the transfer of transmission data bits to the first-out shift memory, and whether the first-in/first-out shift memory becomes "empty";
Alternatively, a line adapter comprising a transmission control circuit for controlling the transmission data bits to be transferred to the first-in/first-out shift memory when a transmission character is set in the buffer register.