JPH03112162A - MOS type semiconductor memory circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is an MO8 type address storage circuit device, particularly an SOI (Silico
MoS type static RAM (hereinafter referred to as SRA
Abbreviated as M. ) regarding.

[Conventional technology]

FIG. 3(a) is a circuit diagram of a memory element of an MO3 type SRAM. In a normal complementary MO8 (0MO8) type SRAM, 3 and 5 are P-type MO8FETs.

4 and 6 are composed of N-type MO8FETs, first CMOS inverters 3 and 4, and second CMOS inverters 5 and 6.
Since the inputs and outputs of the inverters are connected to each other, the feature is that storage operation with bistable properties is possible.

Here, elements 7 and 8 operate to connect the storage element and an external circuit, and are usually composed of N-type MO8FETs. Further, 1 is connected to a power supply potential, and 2 is connected to a ground potential. Third
FIG. 3(b) shows a cross-sectional structure of a first inverter composed of three P-type MO3FETs and four N-type MO8FETs in FIG. 3(a). In highly integrated SRAM, in order to reduce the area occupied by the element, the P-type MO3FET in the element is
OI (Silicon on In5ulator)
It is often composed of In FIG. 3(b), 11 is a P-type silicon substrate, 13 is a gate electrode, and 12A and 12B are both 10
N-type diffusion layer with impurity concentration of 20-10"cm-", 16
are gate insulating films, 13A, 12A, and 12B.

16 constitutes N-type MO8FET 4 in FIG. 3(a). Here, 12A is connected to ground potential 2 in FIG. 3(a). On the other hand, in FIG. 3(b), 15 is a silicon thin film, 14A and 14B are P-type diffusion layers with an impurity concentration of 1019 to 10"cm-3(7) formed in the silicon thin film 15, and 17 is a gate insulator. Membrane 15° 17.14A, 14
In B, the P-type MO3FET 3 in FIG. 3(a) is constructed of SOI. Here, 14A is connected to power supply potential 1 in FIG. 3(a). In FIG. 3(b), 19A is an extraction electrode connected to power supply potential 1, and 19B is a conductor layer for connecting the P-type diffusion layer 14B and the N-type diffusion layer 12B. Furthermore, 18 is an interlayer insulating film, and 13B is a gate electrode of a second inverter composed of P-type MO8FET and 6ON-type MO3FET shown in FIG. 3(a).

[Problem to be solved by the invention]

However, the memory cells according to the above-mentioned known examples have the following drawbacks with respect to the reduction in memory cell area that accompanies the increase in capacity and integration of memories. In other words, trace amounts of uranium U and thorium Th are contained in ceramic materials, microwave materials, and wiring materials used for sealing memory elements.
When the alpha rays generated when the alpha rays decay enter a memory cell, electron-hole pairs are generated along the range of the alpha rays and mix with the charge stored in the storage node, making it impossible to retain information in the memory and causing the information to disappear. will be destroyed. Such development is called a soft error. In conventional static memory, the n+ diffusion layer in the drain region of MO8) transistor and the P
By accumulating enough charge to compensate for the loss of charge due to α rays in the PN junction capacitance formed between the memory cell and the memory cell, and by forming a highly concentrated buried layer directly under the memory cell to narrow the depletion layer, A method for countermeasures against alpha rays has also been proposed. However, when the area of the memory cell is reduced, the stored charge becomes insufficient to compensate for the loss of charge due to α rays, regardless of the measures taken. Therefore, as conventional memory cell structures are miniaturized, the soft error rate increases and the reliability of the memory is also significantly reduced. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and provide a static random access memory that requires a small area and has high resistance to alpha rays.

[Means to solve the problem]

The MO8 type semiconductor memory circuit device of the present invention includes a semiconductor substrate,
A source region and a drain region are provided on the surface of the substrate to be electrically isolated from each other, and a region including at least a portion sandwiched between the source and drain regions is provided with a first insulating film interposed therebetween. A second gate electrode provided on a region including the first gate electrode and electrically connected to the second gate electrode, and a second insulating film provided on the region including the second gate electrode. It has a stacked semiconductor film and a source/drain region that is electrically isolated from each other by a semiconductor portion provided in the semiconductor film and facing the second gate electrode.

MO8 type SRAM having the conventional SOI element mentioned above
In the present invention, the SOI in the memory element is
The gate electrode of the P-type MO8FET, which is an element, is set to have a structure that sufficiently overlaps the P-type drain diffusion layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of one embodiment of the present invention.

11 is a P-type silicon substrate, 13 is an n-type gate polysilicon electrode, and 20 is a metal silicide electrode such as MOS i t, WSiz, Ti5iz, etc. 13 and 20 constitute the polysilicide gate of the N-type MO3FET.

A metal silicide electrode 21 similar to 20 is provided on the silicide electrode 20 and is electrically connected to the silicide electrode 20. 15 is a silicon thin film, 14A, 14B
is 1019~10'' formed in a silicon thin film of 15
P-type diffusion layer with impurity concentration of cm-3, 17 is a gate insulating film, 15.17, 21.14A.

14B constitutes a P-type MO8FET with SOI.

Here, the silicide electrode 21 is connected to the P-type diffusion layer 14 which is the drain of the P-type MO3FET via the gate insulating film 17. B
The overlap area is much larger than that of the conventional case, and the overlap capacity in this area can be increased. Therefore, more charge can be accumulated to compensate for charge loss due to α rays than in the conventional structure, and resistance to α rays is improved. Further, according to the structure of the present invention, the resistance of the common gate electrode of the N-type MOSFET and the P-type MO3FET (7) can be reduced, and the signal propagation delay time can be reduced. In addition, by using an n-type polysilicon film with a small work function as the gate electrode of the N-type MOSFET and a metal silicide film with a large work function on the P-type M○5FET side, the threshold voltage of both the N-type and P-type MO3FET can be increased. It can be set low, and the channel length can be easily shortened.

FIG. 2 is a longitudinal sectional view of another embodiment of the invention.

This embodiment is an example of application to an SRAM cell having a high resistance load resistance. 11 is a P-type silicon substrate, 13 is an n-type polysilicate electrode, and 20 is Mo5iz.

A polycide gate is constructed with metal silicide electrodes such as WS i, T i S i2 and the like.

12A and 12B both have an N type diffusion layer 16 with an impurity concentration of 1020 to 10"cm-' and a gate insulating film having a diagonal of 20°13.
16. At 12A and 12E, the 4 N-type MOS shown in Fig. 2 (a)
Configure FET. 26 is a high load resistor with one end being an N-type MO
It is connected to the drain diffusion layer 12B of the SFET, and the other end is connected to the power supply potential via the electrode 19. One end of the electrode 27 is connected to the ground potential together with the source diffusion layer 12A of the N-type MOSFET. The polysilicon or metal silicide electrode 27 is connected to the silicide electrode and forms a capacitance with the metal silicide electrode 21 via the thin oxide film 22. This capacitance is shown at 25 in FIG. 2(a).

This capacitance is much larger than the capacitance formed between the gate electrode 20 and the electrode 27 conventionally. Therefore, it is possible to accumulate more charge than the conventional structure to compensate for the loss of charge due to α rays.
Improves line resistance.

〔Effect of the invention〕

As explained above, the present invention provides MO
By setting the metal silicide gate electrode of the P-type MO3FET, which is an SOI element, in the memory element of the 8-type S'RAM to a structure that sufficiently overlaps the P-type drain diffusion layer, charge dissipation due to α rays is reduced more than in the conventional structure. A large amount of complementary charge can be accumulated, improving resistance to alpha rays. Further, according to the structure of the present invention, the resistance of the common gate electrode of the N-type MOSFET and the P-type MO8FET can be reduced to reduce the signal propagation delay time. Furthermore, due to the difference in the work function of the gate electrodes, the threshold voltage can be set low and the channel length can be easily shortened.

[Brief explanation of drawings]

FIG. 1 is a vertical sectional view of the first embodiment of the present invention, FIG. 2(a)
is an equivalent circuit diagram of the second embodiment, FIG. 2(b) is a vertical cross-sectional view of the second embodiment, and FIG. 3(a) is a conventional CMO8 type SRAM.
The equivalent circuit diagram of the cell, FIG. 3(b), is a vertical cross-sectional view of a conventional CMO8 type SRAM cell in which a P-type MO3FET is constructed of SOI. 1...Power supply potential, 2...Ground potential, 3
, 5...P-type MO8FET, 4, 6, 7.8.
...N-type MOSFET, 9...Word line, 10...Digital line, 11...P-type semiconductor substrate, 12A, 12B... N-type diffusion layer,
13A, 13B...Polysiligate electrode, 14
A, 14B...P-type diffusion layer, 15...
Silicon thin film, 16.17...gate oxide film,
18...Interlayer insulating film, 19A, 19B...
... Extraction electrode, 20, 21... Metal silicide electrode, 22... Capacitive insulating film, 23, 24.
26...High load resistance, 25...Capacity,
27... Polysilicon or metal silicide electrode.

Claims (1)

[Claims] A semiconductor substrate, source and drain regions provided electrically isolated from each other on the surface of the substrate, and a first insulating film over a region including at least a portion sandwiched between these source and drain regions. a first gate electrode provided; a second gate electrode provided on a region including the first gate electrode and electrically connected to the first gate electrode; a semiconductor film stacked on a region including a second insulating film via a second insulating film, and a source and a drain provided on this semiconductor film and electrically isolated from each other by a portion of the semiconductor film facing the second gate electrode. A stacked semiconductor device comprising a region