JPH03112208A - Automatic gain controlling amplifier circuit - Google Patents
Automatic gain controlling amplifier circuitInfo
- Publication number
- JPH03112208A JPH03112208A JP25008889A JP25008889A JPH03112208A JP H03112208 A JPH03112208 A JP H03112208A JP 25008889 A JP25008889 A JP 25008889A JP 25008889 A JP25008889 A JP 25008889A JP H03112208 A JPH03112208 A JP H03112208A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- output
- mixer
- agc amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000605 extraction Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は無線ＰＣＭ通信機器に用いられる自動利得制御
（ＡＧＣ）増幅回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to automatic gain control (AGC) amplifier circuits used in wireless PCM communication equipment.
第２図に従来の同期検波方式４相ＰＳＫ波復調器に用い
たＡＧＣ増幅回路の一例を示す。図において、入力端子
１４より印加された４相ＰＳＫ波信号はＡＧＣ増幅器１
により出力電力が一定に保たれてミキサ２に印加される
。他方、副搬送波発振器８により発生された副搬送波信
号は２分岐され、一方はそのまま、他方はπ／２移相器
７を介した上でそれぞれミキサ２に印加される。ミキサ
２の出力信号は夫々低域通過フィルタ３．アナログ−デ
ジタル変換器（Ａ／Ｄ変換器）４．論理処理部６を介し
てデータ信号が復調され、それぞれ出力端子１４．１５
から出力される。FIG. 2 shows an example of an AGC amplifier circuit used in a conventional synchronous detection type four-phase PSK wave demodulator. In the figure, the 4-phase PSK wave signal applied from the input terminal 14 is transmitted to the AGC amplifier 1.
The output power is kept constant and applied to the mixer 2. On the other hand, the subcarrier signal generated by the subcarrier oscillator 8 is branched into two branches, one of which is applied as is, and the other is applied to the mixer 2 after passing through the π/2 phase shifter 7. The output signals of mixer 2 are filtered through low-pass filters 3 and 3, respectively. Analog-digital converter (A/D converter)4. The data signals are demodulated via the logic processing unit 6 and output to output terminals 14 and 15, respectively.
is output from.
この場合、低域通過フィルタ３から分岐された信号は全
波整流器５により整流され帯域通過フィルタ９．ミキサ
１０．同期信号発振器１１により同期信号が再生されて
論理処理部６に印加される。In this case, the signal branched from the low-pass filter 3 is rectified by the full-wave rectifier 5 and is then rectified by the band-pass filter 9. Mixer 10. A synchronizing signal is reproduced by the synchronizing signal oscillator 11 and applied to the logic processing section 6.
また、ＡＧＣ増幅器１においては、その出力電力がダイ
オード検波器１７により検出され、制御回路１２を介し
て制御信号がＡＧＣ増幅器１に帰還されることで利得が
制御され、出力電力が一定に保たれる。Further, in the AGC amplifier 1, its output power is detected by the diode detector 17, and a control signal is fed back to the AGC amplifier 1 via the control circuit 12, thereby controlling the gain and keeping the output power constant. It will be done.
上述した従来のＡＧＣ増幅回路では、ＡＧＣ増幅器１の
出力制御をＡＧＣ増幅器１自身から出力される電力を検
出して行っているため、その後段に設けられたミキサ２
．低域通過フィルタ３．７Ａ／Ｄ変換器４における乗積
特性、振幅特性の変動に対しては補正が行えず、復調出
力の電力が変動しデータ誤りが発生しゃずいという問題
がある。In the conventional AGC amplifier circuit described above, the output of the AGC amplifier 1 is controlled by detecting the power output from the AGC amplifier 1 itself.
．． There is a problem in that it is impossible to correct fluctuations in the product characteristics and amplitude characteristics in the low-pass filter 3.7 A/D converter 4, and the power of the demodulated output fluctuates, causing data errors.
本発明の目的は、このような回路後段における特性変動
によるＡＧＣの変動を防止したＡＧＣ増幅回路を提供す
ることにある。An object of the present invention is to provide an AGC amplifier circuit that prevents AGC fluctuations due to characteristic fluctuations in the latter stage of the circuit.
本発明のＡＧＣ増幅回路は、ＡＧＣ増幅器で増幅され、
かつ分岐されてそれぞれミキザ、フィルタ等を通して得
られた２つの直交したベースバンド信号の一部を全波整
流する全波整流器と、これらの整流された信号の電力和
を取る電力和回路と、この電力和を制御信号としてＡＧ
Ｃ増幅器の利得を制御する制御回路とを備えている。The AGC amplifier circuit of the present invention is amplified by an AGC amplifier,
a full-wave rectifier that performs full-wave rectification of a part of two orthogonal baseband signals that are branched and obtained through mixers, filters, etc., and a power summation circuit that calculates the power sum of these rectified signals. AG using power sum as control signal
and a control circuit that controls the gain of the C amplifier.
この構成によれば、ミキサ、フィルタを通った後の信号
に基づいてＡＧＣ増幅器の利得制御を行なうことになり
、ミキサやフィルタにおける振幅特性等の変動に対応し
たＡＣ，Ｃ増幅器の利得制御が可能となる。According to this configuration, the gain of the AGC amplifier is controlled based on the signal that has passed through the mixer and filter, making it possible to control the gain of the AC and C amplifiers in response to fluctuations in amplitude characteristics, etc. in the mixer and filter. becomes.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明を同期検波方式４相ＰＳＫ波復調器に用
いたＡＧＣ増幅回路の一実施例のブロック図であり、第
２図と同一部分及び均等な部分には同一符号を付しであ
る。FIG. 1 is a block diagram of an embodiment of an AGC amplifier circuit using the present invention in a synchronous detection type four-phase PSK wave demodulator, and the same or equivalent parts as in FIG. 2 are given the same reference numerals. be.
第１図において、入力端子１４より印加された４相ＰＳ
Ｋ波信号はＡＧＣ増幅器１で増幅され、分岐された上で
それぞれミキサ２．低域通過フィルタ３．Ａ／Ｄ変換器
４．論理処理部５を経て出力端子１５．１６から出力さ
れる。ミキサ２においては、副搬送波発振器８の出力を
、一方はそのまま、他方はπ／２移相器７を介してそれ
ぞれ入力させている。In FIG. 1, the 4-phase PS applied from the input terminal 14
The K-wave signal is amplified by AGC amplifier 1, branched, and then sent to mixer 2. Low pass filter 3. A/D converter4. It passes through the logic processing section 5 and is output from the output terminals 15 and 16. In the mixer 2, one of the outputs of the subcarrier oscillator 8 is input as is, and the other is inputted through the π/2 phase shifter 7.
また、前記低域通過フィルタ３を経た直交する２つのベ
ースバンド信号はそれぞれ全波整流器５により検波され
、かつ電力和回路１３により合成される。この合成信号
は本来同期信号抽出用として利用されているが、この合
成信号を前記ＡＧＣ増幅器１を制御する制御回路１２に
入力することで、この制御回路１２におけるＡＧＣ増幅
器１の制御信号としても利用できる。Further, the two orthogonal baseband signals that have passed through the low-pass filter 3 are each detected by a full-wave rectifier 5 and combined by a power summation circuit 13. This composite signal is originally used for extracting a synchronization signal, but by inputting this composite signal to the control circuit 12 that controls the AGC amplifier 1, it can also be used as a control signal for the AGC amplifier 1 in this control circuit 12. can.
ここで、全波整流器５・の出力信号によりＡＧＣ増幅器
１が制御される動作原理について説明する。Here, the operating principle in which the AGC amplifier 1 is controlled by the output signal of the full-wave rectifier 5 will be explained.
入力端子１４より印加される４相ＰＳＫ波搬送波信号を
Ｅ、副搬送波発振器より送出される副搬送波信号をＬと
すると、それぞれ下式で表される。Letting E be the four-phase PSK wave carrier signal applied from the input terminal 14 and L be the subcarrier signal sent out from the subcarrier oscillator, each of them is expressed by the following equations.
Ｅ＝、Ｇ−Ａｃｏｓ （（＋） ｔ＋θ十π／２−ｎ
）ｎ−２Ｂ、＋８２
Ｌ ＝、Ｃｃｏｓ （ωを十θ）
ここで、ＧばＡＧＣ増幅器１の増幅率、Ａ、 Ｃはそ
れぞれ搬送波信号、副搬送波信号の振幅、ωθはそれぞ
れ搬送波信号、副搬送波信号の角周波数、初期位相を表
し、Ｂ、＋及びＢ２は０又は１の２値符号を表す。E=, G-Acos ((+) t+θ1π/2-n
) n-2B, +82 L =, Ccos (ω = 10θ) Here, G is the amplification factor of AGC amplifier 1, A and C are the amplitudes of the carrier signal and subcarrier signal, respectively, and ωθ are the carrier signal and subcarrier signal, respectively. It represents the angular frequency and initial phase of the signal, and B, + and B2 represent binary codes of 0 or 1.
このＥとＬをミキサ２に印加し、さらに低域通過フィル
タ３を通過した後の低周波成分のみの出力Ｒは下式で表
される。After applying these E and L to the mixer 2 and further passing through the low-pass filter 3, the output R of only the low frequency component is expressed by the following formula.
したがって、全波整流器５によって検出される制御信号
は、ＡＧＣ増幅器１の出力電力に比例した制御信号とし
て利用することが可能となる。これにより、ミキサ２．
低域通過フィルタ３を含めた系でのＡＧＣ増幅器１の制
御が可能となり、これらにおける特性の変動がＡＧＣ増
幅器１の利得に影響を与えることが抑制でき、復調出力
の安定化を図ってデータ誤りを抑制する。Therefore, the control signal detected by the full-wave rectifier 5 can be used as a control signal proportional to the output power of the AGC amplifier 1. As a result, mixer 2.
It becomes possible to control the AGC amplifier 1 in a system including the low-pass filter 3, and it is possible to suppress the influence of fluctuations in the characteristics of these components on the gain of the AGC amplifier 1, thereby stabilizing the demodulated output and eliminating data errors. suppress.
〔発明の効果〕
以上説明したように本発明は、同期信号抽出用の全波整
流器の出力信号をＡＧＣ増幅器の利得制御用の信号とし
て用いることにより、Ａ Ｃ，Ｃ増幅器の後段に接続す
るミキサ、フィルタにおける振幅特性の変動に対しても
ＡＧＣ制御を行うことができ、復調電力の変動を抑止し
て安定したデータ信号の復調が実現できる効果がある。[Effects of the Invention] As explained above, the present invention uses the output signal of the full-wave rectifier for synchronization signal extraction as a signal for gain control of the AGC amplifier, thereby improving the efficiency of the mixer connected to the downstream stage of the AC, C amplifier. , AGC control can be performed even with respect to fluctuations in amplitude characteristics in the filter, and there is an effect that fluctuations in demodulation power can be suppressed and stable demodulation of data signals can be realized.
第１図は本発明のＡＧＣ増幅回路の一実施例のブロック
図、第２図は従来のＡＧＣ増幅回路のブロック図である
。
１・・・ＡＧＣ増幅器、２・・・ミキサ、３・・・低域
通過フィルタ、４・・・Ａ／Ｄ変換器、５・・・全波整
流器、６・・・論理処理部、７・・・π／２移相器、８
・・・副搬送波発振器、９・・・帯域通過フィルタ、１
０・・・ミキサ、１１・・・同期信号発振器、１２・・
・制窃１回路、１３・・・電力和回路、１４・・・入力
端子、Ｆ５，１６・・・出力端子、１７・・・ダイオー
ド検波器。FIG. 1 is a block diagram of an embodiment of the AGC amplifier circuit of the present invention, and FIG. 2 is a block diagram of a conventional AGC amplifier circuit. DESCRIPTION OF SYMBOLS 1... AGC amplifier, 2... Mixer, 3... Low pass filter, 4... A/D converter, 5... Full wave rectifier, 6... Logic processing part, 7. ...π/2 phase shifter, 8
...Subcarrier oscillator, 9...Band pass filter, 1
0...Mixer, 11...Synchronizing signal oscillator, 12...
- Plagiarism 1 circuit, 13... Power sum circuit, 14... Input terminal, F5, 16... Output terminal, 17... Diode detector.
Claims (1)
上でそれぞれミキサ、フィルタ等を通して２つの直交し
たベースハンド信号を得るようにしたＰＳＫ波復調器等
の自動利得制御増幅回路において、前記フィルタから出
力される２つの直交したベースバンド信号の一部をそれ
ぞれ全波整流する全波整流器と、これらの整流された信
号の電力和を取る電力和回路と、この電力和を制御信号
として前記自動利得制御増幅器の利得を制御する制御回
路とを備えることを特徴とする自動利得制御増幅回路。1. In an automatic gain control amplifier circuit such as a PSK wave demodulator, in which an input signal amplified by an automatic gain control amplifier is branched and then passed through a mixer, a filter, etc. to obtain two orthogonal base hand signals, A full-wave rectifier that performs full-wave rectification of a portion of two orthogonal baseband signals to be output, a power sum circuit that calculates the power sum of these rectified signals, and a power sum circuit that uses this power sum as a control signal to control the automatic gain. An automatic gain control amplifier circuit comprising: a control circuit that controls the gain of a control amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25008889A JPH0773173B2 (en) | 1989-09-26 | 1989-09-26 | Automatic gain control amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25008889A JPH0773173B2 (en) | 1989-09-26 | 1989-09-26 | Automatic gain control amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03112208A true JPH03112208A (en) | 1991-05-13 |
| JPH0773173B2 JPH0773173B2 (en) | 1995-08-02 |
Family
ID=17202633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25008889A Expired - Fee Related JPH0773173B2 (en) | 1989-09-26 | 1989-09-26 | Automatic gain control amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0773173B2 (en) |
-
1989
- 1989-09-26 JP JP25008889A patent/JPH0773173B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0773173B2 (en) | 1995-08-02 |
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