JPH03220823A - Direct conversion receiver - Google Patents

Abstract

PURPOSE:To effectively block saturation relating to the amplification of a post-stage low frequency amplifier circuit with simple circuit constitution by extracting a DC voltage component from a demodulation signal led out from a mixer, feeding back the DC voltage component to the mixer or the like to suppress the DC voltage offset in the demodulation signal. CONSTITUTION:This receiver is roughly constituted of a high frequency amplifier circuit A amplifying a supplied reception signal Se, a demodulation section B receiving an amplified reception signal Sf coming from the circuit A and outputting demodulation signals Sq, Si and a closed loop control section C extracting the DC voltage component in the demodulation signals Sq, Si, feeding it back to the demodulation section B to suppress the DC voltage offset in the demodulation signals Sq, Si. The demodulation signals Sq, Si are fed to A/D converters 32a, 32b, where the signals are digitized and the result is inputted to a data processing circuit 34, in which the closed loop control feeding back control voltages Cva, Cvb to suppress the DC voltage offset of mixers 14a, 14b via D/A converters 33a, 33b while discriminating the digital signal train from a specific digital signal is implemented and a demodulation output signal So is led out.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a direct conversion receiver employed in pagers, mobile radio telephones, etc. component is extracted, and this DC voltage component is fed back to a mixer etc. to suppress the DC voltage offset in the demodulated signal.Furthermore, when the demodulated signal is a digital signal, the digital signal string of the obtained DC voltage is By controlling the feedback to a mixer etc. by distinguishing it from a specific digital signal train, saturation related to the signal processing of the amplification of the low frequency amplifier circuit in the subsequent stage to which the demodulated signal is supplied can be effectively prevented, and the desired high frequency signal can be achieved. This invention relates to a direct conversion receiver that provides high reception sensitivity.

Conventional technology] Conventionally, the receiving section of a pager, mobile radio telephone, etc.
A so-called direct conversion receiver, which has a high S/N ratio and high sensitivity and has a relatively simple circuit configuration, is used.

Figure 2 shows an example of a direct conversion receiver.

In this example, reference numeral 2 denotes a high frequency amplification circuit to which the received signal Sa is supplied, and a high frequency output signal s branched here.
b is supplied and sends out the demodulated signal of low frequency Q,
A channel section 3 and a channel section 4 are provided. Furthermore, it includes a local oscillator 8 that generates and sends out an oscillation frequency that is substantially the same as the high-frequency output signal sb, and a 90° phase shifter 10. Q channel part 3, mixer 3 in channel part 4
a, 4a, LPF 3b, 4b, and low frequency amplifier circuit 3C
14C and A/D converters 3d and 4d are connected to each other. Furthermore, it has a data processing circuit 6 to which output signals of the A/D converters 3d and 4d are supplied.

The above configuration uses mixers 3a and 4a to generate demodulated signals (output signals).
The well-known direct conversion is performed to derive the high-frequency output signal sb, and the mixer 3a outputs substantially the same oscillation frequency as the high-frequency output signal sb.

4a to directly derive the demodulated signal, and LPF 3b
, 4b remove high frequency and high order components. Further, in order to obtain the desired receiving sensitivity, the low frequency amplification circuit 354c performs amplification, and the signal is supplied from there to the data processing circuit 6 that performs final signal processing, and is subjected to processing equivalent to a discriminator, for example. A demodulated signal So is derived.

1. Problems to be Solved by the Invention] However, in the direct conversion receiver according to the above-mentioned conventional example, high reception sensitivity is desired, and a desired high gain is obtained by increasing the amplification degree of the low frequency amplifier circuit 354c. . Therefore, if a minute DC voltage offset with respect to the carrier wave of the received signal occurs in the output signals of the mixers 3a and 4a, that voltage is greatly amplified by the low frequency amplifier circuits 3c and 4C, and the low frequency amplifier circuit 3cx4c becomes saturated. .

As a result, it has the disadvantage that it is difficult to obtain the desired high receiving sensitivity.

The present invention has been made in view of the above points, and uses a relatively simple circuit configuration to prevent DC voltage offset from occurring in the output signal (demodulated signal) of the mixer. It is an object of the present invention to provide a direct conversion receiver that can effectively prevent saturation related to amplification and obtain a desired high reception sensitivity (gain).

[Means for Solving the Problems 2] In order to solve the problems described separately, the direct conversion receiver of the present invention provides a mixer with at least a received signal and an oscillation signal substantially the same as the received signal from an oscillator to generate a demodulated signal. demodulation means for deriving the DC voltage component; DC component derivation means for extracting the DC voltage component to be punished by the demodulation signal; and closed loop control means for feeding back the DC voltage component to suppress the DC voltage offset in the demodulation signal. It is characterized by being prepared.

Furthermore, the feedback control means is characterized in that it performs control to discriminate a digital signal train corresponding to a DC voltage obtained when the demodulated signal is a digital signal from a predetermined digital signal train and feed it back to the mixer.

[Operation] In the above configuration, a DC voltage component is extracted from the demodulated signal derived from the mixer, and this DC voltage component is fed back to the mixer etc. to suppress the DC voltage offset in the demodulated signal. In this case, control is performed to distinguish a digital signal train corresponding to the DC voltage obtained when the demodulated signal is a digital signal from a specific digital signal train and feed it back to the mixer. This effectively prevents saturation in the signal processing of the amplification operation of the low-frequency amplification circuit at the subsequent stage to which the demodulated signal is supplied, and the desired high reception sensitivity can be obtained.

[Example] Next, an example of the direct conversion receiver according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the overall configuration of the embodiment.

FIG. 1 shows an example in which closed loop control and the like are performed using digital signals. This example includes a high-frequency amplification circuit A that amplifies a received signal Se that is supplied, and an amplified received signal Sf that is derived here.
is supplied to a demodulation unit (corresponding to demodulation means) B which derives demodulated signals Sq and Si, extracts the DC voltage component formed in the demodulated signals Sq and Si, and feeds it back to the demodulation unit B to generate the demodulated signal Sq. , and a closed-loop control section (corresponding to the DC component deriving means and the closed-loop control means) C that suppresses the DC voltage offset in Si.

The demodulator B is configured to be separated into Q/I channel systems, and is supplied with the amplified received signal Sf and directly outputs the low frequency signal (
mixers 14a and 1 that derive demodulated signals) Sga and Sgb;
4b, LPFs 16a and 16b that remove high-order components generated by the mixers 14a and 14b, and demodulated signals Sq,
Low frequency amplifiers 18a and 18b that derive Si, a local oscillator 20 that generates and sends out a local oscillation frequency signal with substantially the same oscillation frequency as the amplified received signal Sf, and a 90° phase shifter that shifts the phase of the local oscillation frequency signal by 90°. It has a phase shifter 22.

Further, the closed loop control section C is configured to be differentiated into a Q/I channel system, and is supplied with the demodulated signals Sq and Si to an A/D converter 32a that derives a digitized signal.
, 32b are provided. Furthermore, the demodulated signals Sq, S
Distinguish the digital signal of i from a specific digital signal sequence and convert the DC voltage offset of mixers 14a and 14b into D/A.
It has a data processing circuit 34 that performs closed loop control to feed back control voltages Cva and Cvb for suppression via converters 33a and 33b, and derives a demodulated output signal S○.

Next, the operation of the embodiment with the above configuration will be explained.

First, the supplied received signal Se is amplified by the high frequency amplifier circuit A. The amplified received signal Sf derived here is branched and supplied to mixers 14a and 14b of demodulator B.

The mixers 14a and 14b are supplied with a local oscillation signal having substantially the same frequency as the amplified reception signal Sf from a local oscillator 18 and a local oscillation signal via a 90° phase shifter 22, respectively, and receive a demodulated low frequency signal of the Q/I channel. Frequency signal Sga.

Sgb is derived. These respective low frequency signals Sga, S
High-order components of gb are removed by LPFs 16a and 16b.

Subsequently, predetermined amplification is performed by low frequency amplifiers 18a and 18b, and demodulated signals Sq and Si are derived.

Here, the demodulated signal 5qS51 is sent to the A/D converters 32a, 3
2b and converted into a digital signal. This A/D
The demodulated signals digitized from the converters 32a and 32b (
Sq, Si) are input to the data processing circuit 34.

The demodulated signals Sq and Si are supplied to a data processing circuit 34, which discriminates a specific digital signal sequence and feeds back control voltages Cva and Cvb via D/A converters 33a and 33b to mixers 14a and 14b. Take control. for example,
The ratio of high logic level to low logic level in a time interval, for example, 1 second, of demodulated signal 5qSSi is calculated.

Then, the high logic level in that proportion is, for example,
If the time ratio is biased to exceed 50%, mixer 1
It is determined that the output DC voltage offsets of the D/A converters 4a and 14b are on the child side, and a signal is output that makes the control voltages CVa and (:vb) sent from the D/A converters 38a and 38b to - (minus).

Further, when the ratio is biased to a low logic level, for example, the time ratio is less than 50%, the mixer 14a
, 14b is biased to one side, and outputs a signal that makes the control voltages Cva, Cvb sent from the D/A converters 33a, 33b + (plus).

By performing such closed loop control processing, the mixer 14 is always
Control is performed so that the long-term average value of the voltage offset of the outputs of outputs a and 14b becomes zero.

In this way, the digital signal Sda with a DC voltage component is generated from the low frequency signals derived from the mixers 14a and 14b.
, Sdb is obtained, and the obtained digital signal 5daSSdb is converted to a control voltage Cva via D/A converters 38a and 38b.
SCvb is returned to mixers 14a and 14b, and mixer 14
The DC voltage offset in the low frequency signal (demodulated signal) derived from signals a and 14b is suppressed. In this case, control is performed to distinguish the digital signals Sda and 5cab from a specific digital signal sequence and feed them back via the mixers 14a and 14b+:D/A converters 38a and 38b. This prevents DC voltage from being input to the subsequent low-frequency amplifiers 18a and 18b to which the demodulated signals Sq and Si are supplied, effectively preventing saturation related to amplification signal processing, and achieving the desired high receiving sensitivity. You will get it.

Note that in this embodiment, the control voltage Cva.

Cvb to mixers 14a, 14b1. : Feedback and DC voltage offset are suppressed, but are not limited to this. Mixers 14a, 14b and D/A converters 33a, 33b
The present invention also includes providing an adder circuit or the like between the two and applying the control voltages Cva and cvb thereto for suppression to obtain the same effect as described above.

In addition, the analog signal demodulated signal Sq, Si to LPF
etc., to extract control voltages (CVa, Cvb), and feed back these control voltages Cva, Cvb to mixers 14a, 14b or low frequency amplifiers 18a, 18b, respectively, to generate demodulated signals Sq, Si derived from mixers 14a, 114b. The present invention also includes suppressing the DC voltage offset in the analog signal processing, that is, performing closed-loop control in analog signal processing.

[Effects of the Invention] As described above, the direct conversion receiver of the present invention has the following effects and advantages. That is, a DC voltage component is extracted from the demodulated signal derived from the mixer, and this DC voltage component is fed back to the mixer or the like to suppress the DC voltage offset in the demodulated signal. In this case, a closed loop control is performed in which the DC voltage obtained when the demodulated signal is a digital signal is discriminated from a specific digital signal sequence and fed back to the mixer.

As a result, in a relatively simple circuit configuration, no DC voltage offset occurs in the mixer output signal (demodulated signal), and no DC voltage is input to the low-frequency amplification circuit in the subsequent stage, allowing signal processing related to its amplification to be performed. saturation is effectively prevented, and the desired high receiving sensitivity (gain) can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of a direct conversion receiver according to the present invention, and FIG. 2 is a block diagram showing the overall configuration of a direct conversion receiver according to the prior art. 14a, 14b...Mixer 16a, 16b・LPF 18a, 18b...Low frequency amplifier 20...Local oscillator 22...90° phase shifter 32a, 32b・A/D transformer 33a , 33 b・D/A converter 34...Data processing circuit A...High frequency amplifier circuit B...Demodulator C...Closed loop control unit Cva, Cvb...Control voltage Se...Received signal Sf ...Amplified received signal Sga, Sgb...Low frequency signal Sq, Si...Demodulated signal Se...Demodulated output signal

Claims (3)

[Claims] (1) Demodulating means for deriving a demodulated signal by supplying at least a received signal and an oscillation signal substantially the same as the received signal from an oscillator to a mixer, and a DC component deriving means for extracting a DC voltage component formed in the demodulated signal. A direct conversion receiver comprising: and closed loop control means for feeding back the DC voltage component to suppress a DC voltage offset in the demodulated signal. (2) In the direct conversion receiver according to claim 1, when the demodulated signal is a digital signal, the closed loop control means distinguishes the obtained digital signal train for the DC voltage from a predetermined digital signal train and feeds it back to the mixer. A direct conversion receiver characterized by performing control. (3) In the direct conversion receiver according to claim 1, the closed loop control means is characterized in that the DC voltage component derived from the DC component derivation means is fed back to the mixer to suppress the DC voltage offset in the demodulated signal. Direct conversion receiver.