JPH03113620A - Key input processor - Google Patents

Abstract

PURPOSE:To prevent a competitive relation even if plural keys are simultaneous ly operated by starting a timer, controlling a key operation part selection means and setting only the key operation part where a key operation is detected while a timer counts for a prescribed time to be effective when the key operation in one of the key operation parts is detected. CONSTITUTION:A priority control means starts the timer when a key operation detection means 3 (4) detects the key operation, controls the key operation part selection means 7 and sets only the key operation part where the operation is detected to be effective while the timer 6 counts for a prescribed time. When the key operation part 1 is operated at first, the key operation detection means 3 detects it and the priority control means 5 controls the key operation part selection means 7 while the timer 6 counts for a prescribed time and preferentially gives the key signal of he key operation part 1 to a processor 8. Thus, competition is prevented even if the key operations are simultaneously executed in plural key operation parts 1 and 2, and an appropriate key input processing is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Al Industrial Field of Application) This invention relates to a key input processing device that receives key signals from a plurality of key operation sections and performs processing according to each key operation.
In particular, the present invention relates to a device that prevents conflicts when a plurality of key operation units are operated simultaneously.

(b) Conventional technology For example, a conventional track recording device that displays a track on a display such as a CRT stores position data sent from a navigation device in a memory, and then retrieves the stored data from the memory. It is read out and displayed on the display.

Compared to the case where an X-Y plotter or the like is used, such a track recording device has the advantage that it can be easily reduced or enlarged, and any position can be displayed on the display screen, making ship maneuvering extremely easy.

In such a track recorder, instructions are given to enlarge, reduce, or move the display range by key operations.

(C) Problems to be Solved by the Invention In conventional track recording devices, a key operation section, a display section, and a control section that performs processing and display control according to the contents of key operations are configured in a single housing. It used to be used by being installed at a specific location inside the mouth, but recently, depending on the purpose of use, only the key operation section and display section can be separated from the main body of the device as a single monitor, and multiple monitors can be connected from one main body. A usage pattern is also being considered in which monitors are installed in different locations. In this case, although the same content is displayed on the display section of each monitor, it becomes possible to check the track record content etc. from the key operation section of any monitor.

This type of usage is similar to the relationship between a computer and a terminal in a so-called computer system, but the latter assumes multi-user or multitasking, and each terminal is used for separate information processing. , the former differs in that the same data such as track data is subject to information processing. Therefore, when the key operation units of a plurality of monitors are operated at the same time, a competitive relationship occurs. For example, key signals are input from multiple key operation units to the main unit in a wired OR manner,
The problem arises that the key code changes.

The above-mentioned problems are not limited to key operations in track recorders;
The same problem occurs in general key input processing devices that receive key signals from a plurality of key operation units and process the same data in response to each key operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a key input processing device that prevents conflict by validating only key operations from one key operation section even when a plurality of key operation sections are operated simultaneously. There is a particular thing.

(d) Means for Solving the Problem The invention according to claim 1 provides a key input processing device that receives key signals from a plurality of key operation sections and performs processing according to each key operation. key operation detection means for detecting an operation; timer means for counting a certain amount of time; key operation section selection means for selectively activating any one of the key operation sections; Priority control means starts the timer when the key operation is detected, and controls the key operation section selection means to enable only the key operation section for which the key operation is detected while the timer is counting a certain period of time. It is characterized by having the following.

Further, the invention according to claim 2 provides a key input processing device that receives key signals from a plurality of key operation sections and performs processing corresponding to each key operation. a key operation detecting means for detecting a key operation, a storage means for storing a key operation section whose use has started, and holding the stored state until a key operation indicating the end of use of the key operation section whose use has been started is performed; a key operation section selection means for selectively activating any one of the key operation sections; and controlling the key operation selection means according to the memory contents of the storage means to enable only the single key operation section that is in use. The invention is characterized in that it is provided with a priority control means for

(01 action An example of the configuration of a key input processing device according to claim 1 is shown in FIG. 1.

In the example shown in FIG. 1, there are two key operation sections 1 and 2, and key operation detection means 3 and 4 detect key operations on key operation sections 1 and 2, respectively. The timer means 6 measures a certain period of time. The key operation section selection means 7 selectively enables either one of the key operation sections 1 or 2 and provides a signal to the processing device 8. The priority control means 5 starts a timer 6 when the key operation detecting means 3 or 4 detects a key operation, and also controls the key operation section selection means 7 to select the key whose operation is detected while the timer 6 is counting a certain period of time. Enable only the control panel. For example, if the key operation section l is operated for the first time, the key operation detection means 3 detects this, and the priority control means 5 controls the key operation section selection means 7 while the timer 6 is counting a certain period of time to operate the key. The key signal of section 1 is given to processing device 8 preferentially. Therefore, even if an operation is performed from the key operation unit 2 while the timer 6 is counting time, the response will not be accepted, and a conflicting state can be prevented. After the predetermined time period determined by the timer 6 has elapsed, the priority status of both the key operating units 1 and 2 disappears, and priority is given to the key operating unit that was operated first.

An example of the configuration of a key input processing device according to a second aspect of the present invention is shown in FIG.

In the example shown in FIG. 2, two key operation units 1 and 2 are provided. The key operation detection means 14 and 16 detect a key operation indicating the start of use of the key operations of the key operation units 1 and 2. Key operation detection means 15 and 17 detect key operations indicating the end of use of key operation units 1 and 2, respectively. The storage means 18 stores the key operation section that has started to be used, and also stores the state of the key operation section that has started to be used until a key operation indicating the end of use is performed. The key operation section selection means 20 selectively enables either one of the key operation sections 1 or 2 to
Give a signal. The priority control means 19 is the storage means 18
The key operation selection means 20 is controlled in accordance with the contents of the key operation selection means 20 to enable only the single key operation section currently in use. For example, when a key operation on the key operation section 1 is started, the key operation detection means 14 detects this, and the storage means 18 stores that the key operation section 1 has started to be used. As a result, the priority control means 19 controls the key operation section selection means 20 to selectively enable only the key operation section 1. Thereafter, when a key operation indicating the end of use of the key operation section 1 (ie, the end key 1) in the example shown in the figure is operated, the key operation detection means 15 detects this, and the storage means 18 indicates that the use of the key operation section 1 has ended. (Cancels the use start state of the key operation unit 1). In this way, the state of the storage means 18 is maintained until a key operation indicating the end of use of the key operation section that has started to be used is performed, so that the key operation section that has started to be used first is given priority. Thereafter, the priority state continues for w1 until a key operation indicating the end of use of the prioritized key operation section is performed.

(f) Embodiment FIG. 3 shows an embodiment of a logic circuit of a key input processing device according to claim 1 of the present invention.

In Figure 3, 32 and 33 are monostable circuits, and ■
When the input of (2) becomes "H" level, the output of (2) becomes "H" level for a certain period of time. ■ is a prohibited input, and ■input is “
If the level is “H”, the ■output is “L” regardless of the state of ■.
Becomes Rubel. If there are any signals as key signals A and B, the signal detection circuits 30 and 31 output them as “H”.
“Level it up.

Now, if the key signal A is generated when both the signal detection circuits 30 and 31 are not detecting the key signal and the outputs of both the monostable circuits 32 and 33 are at "L" level, then
The signal detection circuit 30 detects this and sets its output to "H". Since the output of the monostable circuit 33 is "L" level and the output of the inverter 38 is "H" level, the output of the AND gate 36 is "H" level, and the monostable circuit 32
The output remains at "H" level for a certain period of time. Therefore A N
A key signal A is output from the D game I.34, and a key signal is output via the OR gate 40. Even if key signal B is generated in this state, the output of monostable circuit 32 will be “H”.
” level, the output of the inverter 39 remains at the “L” level, so the output of the AND gate 37 and the output of the monostable circuit 33 also remain at the “L” level.As a result, the AN
The output of the D gate 35 remains at the "L" level, and the key signal B becomes invalid. Thereafter, unless the key signal A is generated again within the monostable time of the monostable circuit 32, the output of the monostable circuit 32 returns to the "L" level. Therefore, this state becomes the initial state, and key signal A and key signal B
The power generated in the inner light takes priority and becomes effective.

In addition, when key signal A and key signal B occur simultaneously, both monostable circuits 32 and 33 try to be triggered, but the ■ input of monostable circuit 33 becomes "H" level and becomes a prohibited state. Therefore, only the output from the monostable circuit 32 side becomes "H" level, and the key signal A is prioritized.

Next, an embodiment of the key input processing device according to claim 1 using a microprocessor is shown in FIGS. 4 and 5 (A).
Shown in B).

FIG. 4 is a block diagram of its main parts, in which the I10 boat 44 inputs key signals A and B, and the I10 boat 45 inputs key signals A and B.
outputs control signals to AND gates 41 and 42, respectively. When the signal detection circuit 30 detects the generation of the key signal A, it sets its output to "H" level, and the signal detection circuit 31
When it detects the generation of key signal B, it sets its output to "H" level. I10 when the priority status has not yet been determined
The outputs a and b of the board 45 are both at the "H" level, and when the key signal is generated, the output of the signal detection circuit 30 and the output of the AND gate 41 are at the "H" level, and the output is sent to the CPU via the OR gate 43. An interrupt signal is given to Further, when the key signal B is generated, the signal detection circuit 31
The output of the AND gate 42 becomes I('' level, and an interrupt signal is given to the CPU via the OR gate 43.

FIG. 5(A) is a flowchart showing the CPU interrupt processing procedure caused by the generation of key signal A or key signal B. First, set and start the timer interrupt time so that the timer interrupt occurs after a certain period of time (nl)
. Next, the contents of the I10 port 44 are read, it is detected which of the key signals A and B caused the interrupt, and priority is given to the side where the key signal was generated. That is, for example, when key signal A is generated, signal a is set to "H" level, and when key signal B is generated, signal a is set to "H" level.
” Set I10 port 45 to level (n
2-=n3). For example, if key signal A is generated first, signal a becomes "H" level, and thereafter, an interrupt is generated every time key signal A is generated, and even if key signal B is generated, it is invalid.

FIG. 5(B) is a diagram showing the above-mentioned timer interrupt processing, in which the I10 is set such that both signals a and b go to the "H" level when a certain period of time has elapsed since the generation of the key signal A or the key signal B. Set port 45 (n4). As a result, an interrupt occurs even if either the key signal A or the key signal B occurs again, and the one that occurs first takes priority.

Next, FIG. 6 shows an embodiment of a logic circuit of a key input processing device according to claim 2 of the present invention.

In FIG. 6, the detection circuit 50 detects whether the key signal A is a key operation indicating the end of use of the key operation unit, and when detecting the key operation indicating the end of use, the signal d is set to "H" level. When another key operation is detected, the signal C is set to "H" level. Similarly, the detection circuit 51 sets the signal f to the "H" level when it detects a key operation indicating the end of use of the key operation section from the key signal B, and sets the signal e to the "H" level when detecting any other key operation. .

54 and 55 are flip-flops, and both are in a reset state in the initial state.

Now, when the use of the A-side key operation section is started, the detection circuit 50 sets the signal C to the "H" level.

Since the Q output of the flip-flop 55 is at the "H" level, the output of the AND gate 52 is at the "H" level and the flip-flop 54 is sent.

As a result, key signal A is outputted via AND gate 56 and OR gate 58. At this time, since the Q output of the flip-flop 55 is at the "L" level, the output of the A N D gate 57 is always at the "L" level and the key signal B
becomes invalid. After that, if a key operation indicating the end of use of the key operation section on the A side is performed, the detection circuit 50 outputs the signal C as "
The flip-flop 54 is reset to the initial state.

Finally, FIG. 7 shows a microprocessor-based embodiment of the key input processing device according to claim 2 of the present invention.
3 is a flowchart showing the interrupt processing procedure of FIG. Note that the block configuration is the same as that shown in FIG. 4, so the explanation will be made with reference to this. First, the state of the I10 boat 44 is read, and it is determined which key operation section the operated key is, and it is also determined whether the operated key is a key operation indicating the end of use (nlo-nil). If the key operation does not indicate the end of use, priority is given to the key operation unit on the side where the key operation was performed. That is, for example, if the key operating section on the A side is operated, the signal a will be at the "H" level, and if the key operating section on the B side is operated, the signal a will be at the "H" level. Set I10 port 45 (n12). Therefore, from now on, an interrupt will be generated only by the operation of the key operation unit on the priority side. After that, when a key operation indicating the end of use is performed, the I10 port 45 is set so that both signal a and signal S are at the "zl" level (n1) → n13
).

(g) Effects of the Invention According to this invention, when key signals from a plurality of key operation sections are received and processing is performed in accordance with each key operation, even if key operations are performed simultaneously from a plurality of key operation sections. There is no conflict, and proper key input processing can be performed by operating the key operation section to which priority is given.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a key input processing device according to claim 1 of the present invention, and FIG. 2 is a diagram showing an example of the configuration of a key input device according to claim 2 of the invention. FIG. 3 is a logic circuit diagram of the key input processing device according to the first embodiment. Fourth
Figures 5(A) and 5(B) are a block diagram of a key input processing device according to the second embodiment and a flowchart showing a processing procedure. FIG. 6 is a logic circuit diagram of a key input processing device according to a third embodiment. FIG. 7 is a flowchart showing the processing procedure of the key input processing device according to the fourth embodiment.

Claims (2)

[Claims] (1) In a key input processing device that receives key signals from a plurality of key operation units and performs processing according to each key operation, the key input processing device includes a key operation detection means that detects the operation of each key operation unit, and a key operation detection means that measures a certain period of time. timer means; key operation section selection means for selectively activating any one of the key operation sections; and starting the timer when a key operation on any of the key operation sections is detected; A key input processing device comprising: priority control means for controlling a selection means to enable only the key operation unit for which the key operation is detected while the timer is counting a certain period of time. (2) In a key input processing device that receives key signals from a plurality of key operation sections and performs processing according to each key operation, a key operation detection means that detects key operations indicating the start and end of use of the key operation section. a storage means for storing the key operation unit whose use has started and retaining the memorized state until a key operation indicating the end of use of the key operation unit whose use has been started is performed; a key operation section selection means for selectively activating the key operation section; and a priority control means for controlling the key operation selection means according to the memory contents of the storage means to enable only the single key operation section in use. A key input processing device characterized in that: