JPH0415687A - Display device control circuit - Google Patents

Abstract

PURPOSE:To prevent the processing of a CPU from being delayed even when a write data buffer is in a full state by providing a control means which performs the processing of the CPU when a signal output means inputs a false response signal and an interruption signal to the CPU. CONSTITUTION:When the write data buffer 5 enters the full state wherein there is no command write area, the time from the full state is counted. When the counted time of the full state of the write data buffer 5 exceeds the permissible time of the CPU 1, a command which is outputted by the CPU 1 is stored in the buffer, and the false response signal 11 indicating the write end of the command and the interruption signal 13 which indicates the execution of the processing to the CPU 1 are outputted. When this interruption signal 13 is inputted to the CPU 1, the CPU 1 performs the processing. Consequently, the processing of the CPU in the full state of the write data buffer can be prevented from being delayed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to display device control circuits that control the display of information on display devices of various computers. The present invention relates to a display device control circuit that prevents delays in processing by a CPU that writes commands and the like of information to be written to a write data buffer.

(Prior Art) Among the various computers mentioned above, for example, industrial computers display characters and figures on a display device as a monitor function to monitor each process of production.
It is in use. A display device control circuit that controls the display of characters and the like on the display device will be explained using a block diagram showing control in FIG. 2.

When displaying the above characters and figures on the display device 29, C
The PU 31 uses a program stored in the memory 33 to write a command for displaying the relevant characters and the parameters for the data of the command into the write data buffer 37 arranged on the LSI 33. When the above command and parameters are written, the write data buffer 37 outputs a response signal 39 to the CPU 31 indicating completion of writing of the command, etc. The commands and parameters written to the write data buffer 37 are as follows:
It is interpreted by a command processing processor (hereinafter referred to as ``briproset'') 41 and output to a drawing display processor 43. When the drawing display processor 43 develops, for example, a straight line indicated by the interpreted command and parameters, the drawing display processor 43 develops the straight line at a predetermined address in the image memory 45. The straight line drawn in the image memory 45 is read out by the display control circuit 47 and displayed on the display device 29.

The process of writing commands and parameters to the write data buffer 37 by the CPU 31 is faster than the process of developing, for example, a straight line, indicated by the commands and parameters in the image memory 45 by the graphic processor 41 and the drawing display processor 43. , the write data buffer 37 is in a full state where commands etc. cannot be written.

When the write data buffer 37 becomes full, the write data buffer 37 cannot output a response signal to the CPU 31 because there is no free space in the buffer, and the CPU 31 also goes into a waiting state, making it difficult to improve the processing speed. There wasn't.

(Problems to be Solved by the Invention) Therefore, in the conventional display device control circuit, especially when filling an arbitrary area with a specified color or developing a complicated figure, the drawing display processor 43 stores data in the image memory 45. It takes time to fill in an arbitrary area or develop a complex figure. During the process of filling an arbitrary area in the image memory 45, the write processor 41 cannot output interpreted commands and parameters to the drawing display processor 43, so the write data buffer
7 full state. When the write data buffer 37 becomes full, the write data buffer 37
Since the response signal 39 cannot be output to the CPU 31, the CPU 31 enters a waiting state for three response signals. During the wait state, the CPU
31 cannot execute the process, which may lead to a decrease in the processing efficiency of the system.

Furthermore, when a figure is developed in the image memory 45,
When the write data buffer 37 becomes full, the briprocessor 41 cannot output the parameters of the figure to the drawing display processor 43, so an abnormality occurs and processing is interrupted, resulting in loss of parameters, etc. There was a problem of decreased system reliability.

The present invention has been made in view of the above, and its purpose is to prevent the CPU from running even when the write data buffer is full.
A display device that improves the processing capacity and reliability of a system by preventing processing delays and reliably retaining commands written to the write data buffer by the CPU from a full state of the write data buffer. The object of the present invention is to provide a control circuit.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a write data buffer into which commands for displaying various information on a display device are written by a CPU, and a write data buffer in which commands for displaying various information on a display device are written. a timer that counts the time when the data buffer is in a full state where there is no area for writing commands from the CPU; and according to the count of this timer, when the time when the write data buffer is in a full state exceeds the permissible time of the CPU, the write data is a buffer that stores a command written by a CPU from a full state of the buffer; and a pseudo buffer that indicates completion of writing a command to the CPU when the full state of the write data buffer exceeds the allowable time of the CPU according to a count of the timer. A signal output means for outputting a response signal and an interrupt signal instructing the CPU to execute a process; and a control means for causing the CPU to execute the process when the signal output means inputs a pseudo response signal and an interrupt signal to the CPU. The main point is that it has the following.

(Operation) In the display device control circuit having the above configuration, when the write data buffer into which commands for displaying various information on the display device are written by the CPU becomes full with no area to write the commands, the write data Counts the time since the buffer was full. By counting, the time when the write data buffer is in a full state is determined by the CPU.
When the allowable time has elapsed, the commands output by the CPU from the full state of the write data buffer are stored in the buffer. Further, when the full state time of the write data buffer exceeds the permissible time of the CPU, a pseudo response signal indicating completion of writing the command and an interrupt signal instructing the CPU to execute processing are output to the CPU. When this interrupt signal is input to the CPU, the CPU executes processing. This can prevent delays in CPU processing due to the full state of the write data buffer.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing control of an embodiment of the display device control circuit of the present invention.

The display device control circuit controls the display of characters and figures, such as circles, arcs, straight lines, rectangles, and filled shapes, on the display devices of various computers, such as industrial computers, and controls the display of characters and figures, such as circles, arcs, straight lines, rectangles, and filled shapes, when the write data buffer 5 is in a full state. C.P.
This prevents delays in UI processing.

The CPU 1, which controls the entire display device control circuit, writes commands for displaying characters and figures to be displayed on the display device 27, which will be described later, and parameters indicating the data of the commands, into the write data buffer 5, which will be described later.

The memory 3 stores programs and the like that indicate the operations of the CPUI.

The write data buffer 5 stores commands and parameters written by the CPUI.
When a command or the like is written from the PUI, a response signal 7 indicating completion of writing is output to the response signal monitoring circuit 9.

The response signal monitoring circuit 9 (timer, signal output means, control means) outputs the response signal 7 output from the write data buffer 5 to the CPUI. Write data buffer 5
When a full state is detected in which there is no free space for writing commands and parameters, a timer (not shown) provided inside the response signal monitoring circuit 9 counts the time from the full state. When the time counted by the timer exceeds the allowable time of the CPUI, the response signal monitoring circuit 9 outputs a pseudo response signal 11 indicating completion of writing of the command and parameters to the CPUI. The response signal monitoring circuit 9 also outputs an interrupt signal 13 to the CPUI that causes the CPUI to execute processing.

Here, the permissible time of the CPU 1 is between the general waiting time and the monitoring time of the CPU 1, for example, 50 m5ec.
This is a value that varies depending on the system to which the display device control circuit of the present invention is applied.

The CPU determines that writing is complete by receiving the pseudo response signal 11, releases the wait state by receiving the interrupt signal 13, and commands instructions such as characters and graphics to be displayed on the display device 27, which will be described later. and starts processing such as writing parameters to the write data buffer 5.

The CPUI, memory 3, write data buffer 5, and response signal monitoring circuit 9 transmit commands, parameters, etc. via a common bus 5.
A temporary buffer 17 is connected to. - The time buffer 17 changes from the full state of the write data buffer 5 to
Commands and parameters that are not written to the write data buffer 5 by I are stored. When the write data buffer 5 becomes full, the buffer 7 transfers commands and parameters stored in the common bus 15 to the common bus 15 by a write signal from the response signal monitoring circuit 9.
5. Remember the commands and parameters above.

A command processing processor (hereinafter referred to as briprocessor) 19 interprets the command and parameters written in the write data buffer 5 and outputs them to the drawing display processor 21.

The drawing display processor 21 develops, for example, a straight line in the image memory 23, which is indicated by the interpreted commands and parameters input from the graphics processor 19.

The above-mentioned drawing display processor 21 and briprocessor]9
The dedicated firmware enables high-speed drawing of figures, etc., and has a display function with high throughput (processing efficiency).

In the image memory 23, characters and figures indicated by a command or the like are developed at a predetermined address by the drawing display processor 21. The display control circuit 25 includes the image memory 2
The characters, figures, etc. drawn on 3 are read out and displayed on the display device 27.
Output to. The display device 27 displays characters, figures, etc. read out by the display control circuit 25.

Next, the operation of this embodiment will be explained.

First, after turning on the power to the device, the CPUI writes commands and parameters indicating characters and graphics to be displayed on the display device 27 into the write data buffer 5.

If the write data buffer 5 has a free space in which to write a command or the like, the write data buffer 5 outputs a response signal 7, which is output to the CPUI via the response signal monitoring circuit 9. The command and parameters written to the write data buffer 5 are interpreted by the preprocessor]9.
7 and outputs it to the drawing display processor 2]. The drawing display processor 21 develops, for example, a straight line, indicated by the command and parameters interpreted by the graphic processor 19, in the image memory 23. Display control circuit 2 for expanded straight lines
5 reads out and outputs it to the display device 27, and the display device 2
7, characters and figures are displayed.

By repeating the above operations, the display device 27 displays characters, figures, etc. indicated by commands and parameters written to the write data buffer 5 from the CPUI.

Next, commands and parameters are written from the CPU to the write data buffer 5 at high speed, and when the write data buffer 5 reaches a full state, a timer (not shown) of the response signal monitoring circuit 9 starts the time from the full state. count. When the counted time exceeds the allowable time of the CPUI, for example, 50m5ec, the response signal monitoring circuit 9
By outputting a write signal to the time buffer 17, the write data buffer 5 is changed from the full state to the common bus 15.
The commands and parameters stored above are stored at a predetermined address in the temporary buffer 17. The response signal monitoring circuit 9 also outputs a pseudo response signal 11 indicating completion of writing of a command, etc., and an interrupt signal 13 of a command to start processing of the CPUI. The CPUI, which has been released from the wait state from the full state of the buffer 5 by the pseudo response signal 11 and the interrupt signal 13, sends the write data buffer 5
Executes the process of writing commands, etc.

As a result, even when the write data buffer 5 is in a full state, the CPU can prevent the CPU from being in a waiting state for a long time, thereby preventing a drop in processing efficiency of a system to which the display device control circuit of the present invention is applied. .

Furthermore, even when the write data buffer 5 is full, the CPU
3 are stored in the temporary buffer 17, the processing of characters and the like developed in the image memory 23 by the drawing/display processor 2 is not interrupted.

Of course, this embodiment is applicable not only to industrial computers but also to various types of computers.

[Effects of the Invention] As explained above, according to the present invention, even when the write data buffer is in a full state, delays in CPU processing can be prevented, and the CPU can perform the write operation from the full state of the write data buffer. By ensuring that commands written to the data buffer are retained, system throughput and reliability can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing control of an embodiment of a display device control circuit of the present invention, and FIG. 2 is a block diagram showing control of a conventional display device control circuit. ]... CPU 5... Write data buffer 7 7... Response signal 9... Response signal monitoring circuit 11... Pseudo response signal 13... Interrupt signal 15... Common bus 17... -time buffer

Claims (1)

[Claims] Commands for displaying various information on a display device are
A write data buffer written by the PU, a timer that counts the time when this write data buffer is in a full state where there is no area for writing commands from the CPU, and a timer that counts the time when the write data buffer is in a full state by counting the timer. a buffer for storing a command written by the CPU from a full state of the write data buffer when the allowable time of the CPU has elapsed; a signal output means for outputting a pseudo response signal indicating completion of writing of a command to the CPU and an interrupt signal instructing the CPU to execute a process when the time elapses; and a pseudo response signal and an interrupt signal input to the CPU by the signal output means. A display device control circuit comprising: a control means for causing the CPU to execute processing when the CPU is executed.