JPH03116863A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor jA integrated circuit device, and particularly to a so-called BiMO3, B1CMOS type integrated circuit device in which a bipolar transistor and a MOS +- transistor are mounted together. .

[Prior Art] In this kind of conventional semiconductor integrated circuit device, each transistor is formed in a separate semiconductor region.

That is, in order to realize a circuit consisting of a p-channel MOS transistor (hereinafter referred to as pMos) 10, an n-channel MOS transistor (hereinafter referred to as 0MO5) 20, and an npn bipolar transistor 30 shown in FIG. As shown in FIG.

S20 is formed within the n-type semiconductor region 42.

pMos ] O is source region 11, drain region 1
The nMO 820 has a source region 21, a drain region 23, and a gate electrode 22, and a bipolar transistor 3o.
is a p-conductivity type base region 31 formed in an n-type semiconductor region 43 serving as a collector region, and the base region 31
It has an n+ type emitter region 32 formed therein. The collector extraction region 33 is in contact with an n + -type buried layer 34 formed under the n-type semiconductor region 43 .

The source region 11 of the 9MO 310 is an n-type semiconductor region 45
The drain region 13 of the 9MO 310 is connected to the ■po power supply via the metal wiring 51 together with the n+ type semiconductor region 46 formed within the n+ type semiconductor region 43 and the n+ type collector extraction region 33 formed within the n type semiconductor region 43. , is connected to the drain region 23 of the nMO 320 and the base region 31 of the bipolar transistor 30 by a metal wiring 53a. In addition, the source region 2 of the nM OS 20
1 is grounded by a metal wiring 54 together with a ρ1 type half-body region 44 formed in the n-type semiconductor region 42 . Gate electrode 12 of pMos 10 and nMOS
The gate electrode 22 of No. 20 is connected to the input terminal In via a polysilicon wiring 55, and the emitter region 32 of the bipolar transistor is connected to the output terminal Out via the metal wiring 52.

[Problems to be Solved by the Invention] In the conventional integrated circuit device described above, since the 9MO8 and the bipolar transistor are formed in separate regions separated by a p-type semiconductor region, it is difficult to separate the two regions. It is necessary to secure the width of the p-type semiconductor region at a certain level or more, and the distance between the p-type semiconductor region and the diffusion region of each transistor must be set at a certain level or more. It does not require a large area on a chip to form.

[Means for Solving the Problems] In the semiconductor integrated circuit device of the present invention, an MO8I-transistor is formed in the collector region of a bipolar transistor, and the drain region of the MoS transistor is in contact with the base region of the bipolar transistor. It is forced and unified.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1(a) is a plan view showing one embodiment of the present invention, and FIG. 1(b) and FIG. 1(c) are respectively FIG. 1(a).
) is a sectional view taken along line B-B' and line c-c'. Also, the first
An equivalent circuit diagram of the figure is shown in FIG.

In FIG. 1, parts equivalent to those in the conventional example in FIG.
n which is the collector region of the n bipolar transistor 30
As shown in FIG. 1(b), the drain region 13 of the 9MO8 and the base region 31 of the bipolar transistor are in contact with each other to form an integrated region. This configuration eliminates the need for an n-type semiconductor region (46 in FIG. 3) for applying a well potential to the region where 9MO8 is formed. In addition, the base electrode is no longer required (in this example, the drain electrode of pMOs also serves as the base electrode), and the drain region 13 of 9MO3,
(2) The metal wiring 53 connecting the drain region 23 of the MOS and the base region of the bipolar transistor is simplified.

f) By creating the MOS and bipolar transistor in the same region, the p-type semiconductor region (separation region) between the two regions, which was required when both transistors were formed in separate regions, is no longer required. Since it is no longer necessary to secure a certain distance from this isolation region to the diffusion region of each transistor, the drain 6 of 9MO8
Since the page area and the base area of the bipolar transistor can be integrated, the area required to form both transistors can be significantly reduced.

Although the above embodiments have been described with reference to 9MO8 and npn bipolar transistors, the present invention can produce similar effects even if their conductivity types are reversed.

[Effects of the Invention] As explained above, in the present invention, a MoS transistor and a bipolar transistor are built in the same region, and the drain region of the MOS transistor and the base region of the bipolar transistor are integrated. According to the present invention, the area required for isolation can be made unnecessary, and the area required to form both transistors can be significantly reduced. Further, according to the present invention, the number of contacts can be reduced and the wiring can be simplified, so that semiconductor IA integrated circuit devices can be manufactured at low cost and with high yield.

[Brief explanation of drawings]

FIG. 1 (a> is a plan view showing one embodiment of the present invention;
Figure (b) and Figure 1 (c) are respectively the BB' line,
3 is a plan view showing a conventional example, and FIG. 2 is an equivalent circuit diagram of the apparatus shown in FIGS. 1 and 3. 10...p channel MOS transistor, 20...
n-channel MO8 transistor, 11.21... source region, 12.22... gate electrode,
13.23...Drain region, 30...NPN bipolar transistor, 31...Base region, 3
2... Emitter region, 33... Collector extraction region, 34... N1 type buried layer, 41.
...p-type semiconductor substrate, /]2...n-type semiconductor region,
43.45...n-type semiconductor region, 44...
p+ type semiconductor region, 46... n1 type semiconductor region,
51-54.53a...metal wiring, 55...
Polysilicon wiring.

Claims (1)

[Claims] In a semiconductor integrated circuit device having a bipolar transistor and a MOS transistor, a source and drain region of a second conductivity type of the MOS transistor are formed in a semiconductor region of a first conductivity type serving as a collector region of the bipolar transistor, and The drain region of the MOS transistor is the second region of the bipolar transistor.
A semiconductor integrated circuit device, characterized in that it is formed in contact with a conductive type base region.